Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-05-06
2003-10-28
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185250
Reexamination Certificate
active
06639838
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile memory architecture and to a corresponding integrated circuit. It can be applied especially to EPROM, EEPROM and Flash EPROM type memories.
BACKGROUND OF THE INVENTION
In general, the term non-volatile memory cells must be understood to mean an element capable of memorizing an electrical state, and comprises a control gate with two channel electrodes. A typical example of a non-volatile memory cell comprises a floating-gate MOS transistor. Other types of non-volatile memory cells such as, for example, ferro-magnetic memory cells are known. For clarity of the explanation provided herein, floating-gate MOS transistor memory cells will be used as an example. The two electrodes are then typically the drain and the source of the transistor. The role of these electrodes may be reversed.
A non-volatile memory is typically organized in the form of data banks DATABANK(0) DATABANK(p−1) in a matrix of rows Row
0
to Row
n−1
and columns Col
0
to Col
p−1
, a known exemplary embodiment of which is shown in FIG.
1
. In this example, each word has several memory cells grouped together in the same row, and comprises a selection transistor connected to the corresponding row and to the corresponding column. The control gates of the cells of a word are connected in common. Their drains (or their sources) are connected to respective bit lines. Each bit line connects all the drains (or all the sources) of the same ranking cells in a column. It is to these control gates and to these drains that the high-voltage levels needed for the programming of the cells are to be applied.
The selection of a word in a bank of the matrix is-done by the control gate common to the control gates of the memory cells of the word, and by their drains (or their sources) which form the bit lines. Thus, in these architectures, the high-voltage switching and selection functions are linked. For these reasons, the row and column decoders must integrate high-voltage switching circuits, one per column and one per row. Switching circuits associated with the bit lines are also needed. These switches are costly and very bulky.
Furthermore, with regard to the reading of a memory word, it may be recalled that it is usually necessary to plan for a bit line precharging phase. The term precharging must be taken, in the general sense, to mean a charging or discharging of these lines, depending on the memory technology considered. The bit lines play a role in the selection of the memory cells. This precharging phase can be applied only to the bit lines corresponding to the selected word. To successively read several words in the memory (i.e., to carry out multiple readings), the precharging phase must be repeated for each reading. This is very penalizing in terms of reading speed.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to provide a novel memory architecture that does not have the above-mentioned drawbacks. In particular, an object of the present invention is to reduce the number of high-voltage switching circuits in the memory architecture.
Another object of the present invention is to improve the read access time of a memory, namely the amount of time taken for the data reflecting the state stored in one or more memory cells to become available at an output.
These and other objects, advantages and features according to the present invention are provided by a word-based architecture in which the word-selection function is disassociated from the function of the switching of the high-voltage to the memory cells and, more generally, from the function of the application to the memory cells of voltage levels corresponding to the operation to be performed, namely a reading or programming operation.
According to the invention, the word is selected neither by the control gate of the cells nor by the bit lines which connect the drain of these cells. Thus, according to the invention, the application of a high voltage to the drain and control gate of a memory cell is not sufficient to select this cell in the programming mode. More generally, the application of reading or programming levels of a bias voltage to the gates and drains of cells of the memory is not sufficient for these cells to be selected in a reading or programming mode.
The basic idea of the invention lies in the use of the channel electrode which is not connected to the bit lines. In general, it is the source. However, the source/drain functions may be reversed in certain memory architectures.
Thus, according to the invention, in a memory architecture in which the drains are the channel electrodes and are connected to the bit lines, then each memory word has an associated word selection transistor for selection by the source of the cells. This selection transistor using the source is controlled by the low-voltage address selection signals given by the address decoders of the memory (row decoder and column decoder). The term low-voltage logic level is understood to mean a voltage level lower than or equal to the logic supply voltage Vcc of the integrated circuit. This level depends on the technology considered. For example, this level may be equal to Vcc or to ⅔ of Vcc.
In other words, the output signals from the decoders are applied directly to the selection transistors. The function of the high-voltage switching circuits, therefore, is no longer that of applying the high voltage by selecting the word addressed in the write mode but that of applying the high voltage at least to the word selected by the other circuits.
Since the bit lines and the control gates no longer participate in the selection of the word, it becomes possible to group bit lines with one another and control gates with one another so that they can be controlled at high voltage by the same switching circuit. Each switching circuit can thus control several bit lines or control gates that have been pooled together. Thus, the number of high-voltage switching circuits is considerably reduced.
In particular, the same-ranking bit lines of two distinct word columns and/or the control gates of two distinct rows can be grouped together. The application of the high voltage to the bit line or the control gate of a non-selected column will not affect the associated memory cells, since their source is at a floating potential. The selection transistor is not selected and is non-conductive.
Furthermore, since the bit lines are no longer in the selection path of the cells, it becomes possible to launch the precharging phase of the bit lines to read the memorized words for all the bit lines at the same time. Therefore, each read cycle no longer has any precharging phase. This phase is taken out of the read cycle and is performed before this read cycle, only once. In a multiple-reading operation, the speed of access to the memory is thus appreciably improved.
The invention therefore relates to a non-volatile memory architecture organized in words according to a matrix of rows and columns. A word of the matrix is selected by row-selection and column-selection signals given by address decoders. Each word groups together several memory cells in the same row, and each cell comprises a memory effect MOS transistor with a control gate, a first channel electrode and a second channel electrode. The control gates of the cells of each row of the memory are connected in common to a control gate line, and the first electrode of each cell is connected to a respective bit line. Each word comprises a transistor for the selection of the word by the second electrode of each of its cells. The transistor is controlled by the low-voltage address selection signals given at the output by the decoders.
The invention also relates to an integrated circuit comprising a non-volatile memory with an architecture as described above.
REFERENCES:
patent: 5185718 (1993-02-01), Rinerson et al.
patent: 5400276 (1995-03-01), Takeguchi
patent: 5467310 (1995-11-01), Yoshida et al.
patent: 5517044 (1996-05-01),
Dray Cyrille
Fournel Richard
Thomas Sigrid
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Hoang Huan
Jorgenson Lisa K.
STMicroelectronics SA
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