Non-volatile memory apparatus and method with deep N-well

Details Non-volatile memory apparatus and method with deep N-well Non-volatile memory apparatus and method with deep N-well

2011-07-19

2011-07-19

Mai, Son L (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185100, C365S185280, C365S185290, C257S316000, C257S321000, C257S322000

Reexamination Certificate

active

07983081

ABSTRACT:
An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well located in the P substrate, while a P-well and an N-well are located in the deep N-well. The memory cell further includes a PMOS transistor located in the N-well, in which the PMOS transistor includes a PMOS gate-oxide, and an NMOS capacitor located in the P-well. The NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide. The memory cell further includes a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.

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