Non-volatile memory and operating method thereof

Details Non-volatile memory and operating method thereof Non-volatile memory and operating method thereof

2002-08-02

2003-11-11

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185260

Reexamination Certificate

active

06646924

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a non-volatile memory and a method for operating the same. More particularly, the present invention relates to an electrically erasable programmable read-only memory (E
2
PROM) capable of storing two bits in one cell and a method for operating the same.
2. Description of Related Art
E
2
PROM can be programmed, read, and erased repeatedly and can retain data even if disconnected from power supply, and therefore is widely used in personal computers and electronic apparatuses.
A conventional E
2
PROM uses a floating gate and a control gate both made from doped polysilicon, and is programmed by injecting charges into its floating gate. Since doped polysilicon is electrically conductive, the charges distribute evenly in the floating gate after programming. Consequently, a leakage easily occurs in the memory cell if there are defects in the tunnel oxide layer under the floating gate, and the reliability of the device is thus lowered.
To solve the leakage problem of the conventional E
2
PROM, a charge-trapping layer is recently developed to replace the polysilicon floating gate in the conventional flash memory. The charge-trapping layer usually comprises a silicon nitride layer that is disposed between two silicon oxide layers to form an oxide
itride/oxide (ONO) composite layer, while the memory with a nitride charge-trapping layer is known as a “nitride read-only memory (NROM)”. In an NROM, the nitride charge-trapping is able to trap charges so that the injected charges will not distribute evenly in the charge-trapping layer, but will be localized in a region of the charge-trapping layer near the charge injection side. Because the injected charges are localized, the charge-trapping region is small and is less likely to locate on the defects of the tunnel oxide layer. A leakage therefore does not easily occur in the device.
Besides, since charges are localized in a region of the charge-trapping layer near the drain or the source, the NROM is capable of storing two bits in one memory-cell. This is achieved by, for example, changing the direction of channel current and thereby varying the generating site and the injecting region of hot electrons as the channel hot electron injection (CHEI) mechanism is used for programming. Particularly, if a higher bias is applied to the first source/drain region of the memory cell, hot electrons will be generated and be injected into the charge-trapping layer near the first source/drain region. Similarly, if a higher bias is the applied to the second source/drain region, hot electrons will be generated and be injected into the charge-trapping layer near the second source/drain region. Thus, a memory cell can be configured into one of the four states, in which each of the two ends of the charge-trapping layer may have one group of electrons or have zero electron trapped in it.
FIG. 1
illustrates a local circuit diagram of a NROM in the prior art, which is also disclosed in U.S. Pat. No. 5,966,603. The example illustrated in
FIG. 1
is a 3×3 array that includes memory cells Qn
1
~Qn
9
coupled to word lines WL
01
~WL
03
, bit lines BL
1
and BL
2
, and source lines SL
1
and SL
2
. The drains of Qn
1
, Qn
4
and Qn
7
are coupled to BL
1
, and the drains of Qn
2
, Qn
3
, Qn
5
, Qn
6
, Qn
8
and Qn
9
are coupled to BL
2
. The sources of Qn
1
, Qn
2
, Qn
4
, Qn
5
, Qn
7
and Qn
8
are coupled to SL
1
, and the sources of Qn
3
, Qn
6
and Qn
9
are coupled to SL
2
. The gates of the memory cells in the same row are connected to a word line, i.e., the gates of Qn
1
~Qn
3
are coupled to WL
01
, the gates of Qn
4
~Qn
6
to WL
02
, and the gates of Qn
7
~Qn
9
to WL
03
.
Refer to
FIG. 1
, in each row of memory cells, the gates of the cells are coupled to the same word line, each cell shares its source and drain with two adjacent cells, and the sources (or drains) of the cells are coupled to different source lines (or bit lines). Therefore, it is necessary to apply different biases to different source lines or bit lines as a specific memory cell is to be programmed, and the programming process is quite complicated.
For example, when the source side of Qn
5
is being programmed, WL
02
, SL
1
and BL
2
are applied with 5V, 5V and 0V, respectively, to induce band-to-band hot hole phenomenon and thereby inject hot holes into the charge-trapping layer on the source side. However, when the source side of Qn
5
is being programmed, the bit line BL
1
coupled to Qn
4
must be applied with 3V to prevent programming of Qn
4
since Qn
4
and Qn
5
both are coupled to WL
02
and SL
1
. Similarly, when the drain side of Qn
5
is being programmed, WL
02
, BL
2
and SL
1
are applied with 5V, 5V and 0V, respectively, to induce band-to-band hot hole phenomenon and thereby inject hot holes into the charge-trapping layer on the drain side. However, when the drain side of Qn
5
is being programmed, the source line SL
2
coupled to Qn
6
must be applied with 3V to prevent programming of Qn
6
since Qn
6
and Qn
5
both are coupled to WL
02
and BL
2
. Accordingly, the programming process is quite complicated.
Moreover, since the conventional NROM of 2 bits/cell type uses buried bit lines and buried source lines that have high resistance, the operating speed of the memory device cannot be raised.
SUMMARY OF INVENTION
In view of the above mentioned, this invention provides a non-volatile memory and a method for operating the same. In the method, the programming operation of a memory cell does not interfere with other cells, and the memory can be programmed with a bit, a byte or a sector as a unit.
A non-volatile memory of this invention comprises a plurality of memory cells, a plurality of word lines, a plurality of drain lines and a plurality of source lines. Two adjacent memory cells in the same row share a source and are grouped into a cell pair, and all cell pairs are arranged in rows and columns, wherein two cell pairs in the same row share a drain. The sources of the memory cells in the same row are connected to a source line, and the drains of the memory cells in the same row are connected to a drain line. In addition, the gates of the cells in the same column are coupled to a word line.
The non-volatile memory of this invention further comprise a plurality of source line select transistors, a plurality of drain line select transistors, a plurality of source line select lines, a plurality of drain line select lines, a global source line (GSL) and a global drain line (GDL). Each source line select transistor is coupled between the global source line (GSL) and a source line, and the gate of the source line select transistor is coupled to a source line select line. Analogously, each drain line select transistor is coupled between the global drain line (GDL) and a drain line, and the gate of the drain line select transistor is coupled to a drain line select line.
In the non-volatile memory of this invention, the source line and the drain line can comprise a low-resistance material such as metal. Since the sources/drains of the memory cells in the same rows are electrically connected to a source/drain line, the resistance of the memory array is lower and the operating speed is higher as compared with a conventional memory array using buried bit lines and buried source lines.
Moreover, since the non-volatile memory of this memory does not use buried bit lines, the sources/drains can be formed after the word lines are formed and the manufacturing process thus is more compatible with conventional CMOS process.
Furthermore, in this invention, an isolation can be formed between rows of memory cells, and spacers can be formed on the sidewalls of the gates of each memory cell. With the isolation and the spacers, the contacts between the sources/drains and source/drain lines can be formed as borderless contacts.
Moreover, since the source/drain line select transistors in the periphery circuit are coupled to the same global source/drain line, the select transistor array can be formed more comp

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