Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-12-23
2010-10-19
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S191000, C365S207000
Reexamination Certificate
active
07817476
ABSTRACT:
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.
REFERENCES:
patent: 4357685 (1982-11-01), Daniele et al.
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5418752 (1995-05-01), Harari et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5595924 (1997-01-01), Yuan et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5768192 (1998-06-01), Eitan
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6307800 (2001-10-01), Derner
patent: 6396736 (2002-05-01), Jyouno et al.
patent: 7471575 (2008-12-01), Cernea et al.
patent: 2004/0060031 (2004-03-01), Cernea
patent: 2004/0109357 (2004-06-01), Cernea et al.
patent: 2006/0140007 (2006-06-01), Cernea et al.
patent: 2007/0263450 (2007-11-01), Cernea et al.
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 11/026,536 on Apr. 24, 2006, 13 pages.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 11/026,536 on Oct. 20, 2006, 12 pages.
USPTO, “Office Action,” mailed in related U.S. Appl. No. 11/026,536 on Apr. 23, 2007, 13 pages.
Cernea Raul-Adrian
Chan Siu Lung
Khalid Shahzad
Li Yan
Daivs Wright Tremaine LLP
Graham Kretelia
Ho Hoai V
Sandisk Corporation
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