Non-volatile memory and method with reduced source line bias...

Details Non-volatile memory and method with reduced source line bias... Non-volatile memory and method with reduced source line bias...

2007-03-27

2007-03-27

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S205000, C365S203000

Reexamination Certificate

active

10254830

ABSTRACT:
Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In this way, sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells.

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