Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2007-01-30
2007-01-30
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030, C365S185210
Reexamination Certificate
active
11097502
ABSTRACT:
Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
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Cernea Raul-Adrian
Chan Siu Lung
Parsons Hsue & de Runtz LLP
SanDisk Corporation
Weinberg Michael
Zarabian Amir
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