Non volatile memory and data processor

Details Non volatile memory and data processor Non volatile memory and data processor

2003-01-17

2004-09-21

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185130, C365S185180

Reexamination Certificate

active

06795346

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an electrically programmable non-volatile memory, and a data processor. The present invention also relates to a technology for solving a delay in read access due to precharge and discharge operations of each bit line, which are necessary for the operation of reading memory information held in each non-volatile memory cells of the non-volatile memory, e.g., a technology effective for application to a microcomputer equipped with a flash memory in an on-chip form.
A flash memory, which is one electrically writable or programmable memory, has non-volatile memory cells each comprising one memory cell transistor having a floating gate, a control gate, a source and a drain, for example. In the memory cell transistor, a threshold voltage thereof rises when electrons are injected into the floating gate, whereas when the electrons are extracted from the floating gate, its threshold voltage drops. The memory cell transistor serves so as to store information corresponding to the magnitude or high and low levels of a threshold voltage relative to a word line voltage (voltage applied to control gate) for reading data. Although not restricted in particular, the state in which the threshold voltage of the memory cell transistor is low, is called an “erase state”, and the state in which the threshold voltage thereof is high, is called a “write state”.
In order to read information held in each of the non-volatile memory cells, the drain side (bit line side) of the selected non-volatile memory cell is clamped to a precharge voltage and a gate voltage is applied. If the electrons have been stored in the non-volatile memory cell, the threshold voltage is high and no current flows even if the gate voltage is applied. If no electrons are stored in the memory cell, the threshold voltage is low and the current flows when the gate voltage is applied.
A sense amplifier detects such a state. Now consider where the sense amplifier is of a current sense type sense amplifier, for example. When the sense amplifier causes a current equivalent to half of a memory cell current (corresponding to a current flowing in each memory cell held on) to flow, a bit line voltage of a memory cell high in threshold voltage becomes higher than a precharge voltage. A bit line voltage of a memory cell low in threshold voltage becomes lower than the precharge voltage. A logic value of memory information held in the corresponding memory cell is judged according to the difference between the above voltages. Even when the sense amplifier belongs to a non-current sense type configuration, e.g., it is of a differential sense amplifier of such a type that a bit line voltage is compared with a reference level, there is a need to precharge the corresponding bit line to the reference level or a level close to it in advance before the start of a read operation. In order to read the information of the memory cell in this way, there is a need to clamp the corresponding bit line to the precharge voltage.
On the other hand, let's look at the memory cell. If the voltage is always applied to the source side (source line side) or drain side (bit line side), such an electric field that electrons are stored in or extracted or drawn from the floating gate, is formed, thus causing a possibility that memory information will be damaged (disturbed). It is not desirable that the voltage like the precharge voltage is always applied to the drain of each memory cell via its corresponding bit line in order to prevent the fear of such disturb before happens.
Therefore, there is a need to set the source and drain sides of the memory cell as a ground potential when no reading is done. The bit line must be discharged because the precharge voltage is clamped before the reading and the voltages on the source and drain sides are set to the ground potential rapidly after the reading. In order to reduce capacitance parasitic on each bit line connected with the drain of the memory cell in particular, a main/sub bit line structure is frequently adopted. In the main/sub bit line structure, only a sub bit line connected with a memory cell intended for a read operation is connected to its corresponding main bit line.
SUMMARY OF THE INVENTION
However, in order to read memory information of a non-volatile memory cell, there is a need to carry out pre-reading bit line precharge and post-reading bit line discharge. Even if the operating time (corresponding to the time required to make a decision as to whether a main bit line voltage is larger or smaller than a precharge voltage) necessary to read memory information could be shortened owing to the configuration or the like of the sense amplifier, the shortening of the time intervals for the precharge and discharge have been not yet implemented. With the trend toward an increase in parasitic capacitive component due to an increase in storage capacity, the precharge and discharge time intervals become long in reverse.
An object of the present invention is to shorten the time necessary to charge and discharge a bit line to which a non-volatile memory cell is connected.
Another object of the present invention is to speed up the reading of memory information from a non-volatile memory cell without performing an improvement in the performance of a sense amplifier, etc.
A further object of the present invention is to provide a data processor capable of contributing to the speeding up of data processing in terms of the reading of memory information from a non-volatile memory cell at high speed.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
A semiconductor device according to the present invention has an electrically programmable non-volatile memory. The non-volatile memory includes a plurality of non-volatile memory cells (MC), word lines (X
00
through Xkn) respectively connected to select terminals of the non-volatile memory cells, sub bit lines (LB
00
through LBkm) respectively connected to data terminals of the non-volatile memory cells, main bit lines (MB
0
through MBm), sub bit line selection switch elements (Q
00
through Qkm) which selectively connect the sub bit lines to the main bit lines, a sense amplifier (
30
) connected to the main bit lines via column switch elements (QY
0
through QYm), and voltage supply elements (QPC
0
through QPCm) each of which supplies a predetermined clamp voltage to each of the main bit lines. The clamp voltage is a predetermined level between a high-level side attainment level outputted from the sense amplifier and a low-level side attainment level outputted therefrom. Each of the voltage supply elements supplies the clamp voltage to the corresponding main bit line during at least a period prior to and subsequent to a read operation for each of the non-volatile memory cells.
According to the above means, the clamp voltage is supplied from each of the voltage supply elements to its corresponding main bit line during at least the period prior to and subsequent to the read operation for each non-volatile memory cell. Accordingly, there is no need to precharge the main bit line from the ground level upon the operation of reading the memory information, and the read operating time can hence be shortened. Since the non-volatile memory becomes fast in operating speed, the operating speed or throughput of the whole data processing system using it can be enhanced.
The clamp voltage is a level desirable in terms of a sense operation of the sense amplifier. The clamp voltage is, for example, a criterion level of the sense amplifier or a level higher than the criterion level. A discharge for each sub bit line is not necessary either for a non-volatile memory cell having a device structure free of the occurrence of disturb at that level.
In order to stabilize the ope

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