Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2007-10-09
2007-10-09
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185240
Reexamination Certificate
active
11381972
ABSTRACT:
In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.
REFERENCES:
patent: 4357685 (1982-11-01), Daniele et al.
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5418752 (1995-05-01), Harari et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5595924 (1997-01-01), Yuan et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5768192 (1998-06-01), Eitan
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5867429 (1999-02-01), Chen et al.
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6278633 (2001-08-01), Wong et al.
patent: 6288935 (2001-09-01), Shibata et al.
patent: 6522580 (2003-02-01), Chen et al.
patent: 6657891 (2003-12-01), Shibata et al.
patent: 6760257 (2004-07-01), Huang et al.
patent: 6768681 (2004-07-01), Kim
patent: 6781877 (2004-08-01), Cernea et al.
patent: 6845039 (2005-01-01), Chen et al.
patent: 7057939 (2006-06-01), Li et al.
patent: 2004/0047183 (2004-03-01), Tanaka et al.
patent: 2004/0060031 (2004-03-01), Cernea
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, in corresponding PCT/US2005/013018, dated Apr. 8, 2005, 12 pages.
Takeuchi et al., “A Multi-Page Cell Architecture for High-Speed Programming Multi-Level NAND Flash Memories,” 1997 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 1997, pp. 67-68.
Fong Yupin Kawing
Li Yan
Miwa Toru
Davis , Wright, Tremaine, LLP
Hoang Huan
SanDisk Corporation
LandOfFree
Non-volatile memory and control with improved partial page... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile memory and control with improved partial page..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory and control with improved partial page... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3873030