Non-volatile latch circuit that has minimal control circuitry

Details Non-volatile latch circuit that has minimal control circuitry Non-volatile latch circuit that has minimal control circuitry

2002-01-03

2003-10-28

Tran, M. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180

Reexamination Certificate

active

06639840

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit devices and, more particularly, to a non-volatile latch circuit that has minimal control circuitry.
2. Related Art
Semiconductor memory can be classified as either volatile or non-volatile memory. Volatile memory loses its stored information when power is removed from the memory, whereas non-volatile memory retains its stored information when power is removed from the memory. One common type of non-volatile memory is known as a non-volatile latch circuit. A non-volatile latch circuit is capable of storing one bit of data (i.e., a logic 1 or a logic 0).
Non-volatile latch circuits can be classified as non-dedicated control circuitry or dedicated control circuitry non-volatile latch circuits. Non-dedicated control circuitry non-volatile latch circuits are used in applications where many bytes of data (e.g., thousands of bytes) need to be stored. These non-volatile latch circuits are typically arranged in a two-dimensional array and are controlled by control circuitry that is shared by each of the non-volatile latch circuits. For example, row and column decoder circuitry is shared by each of the non-volatile latch circuits in the array. An example of an integrated circuit device that uses these non-volatile latch circuits is an electrically erasable programmable read-only memory (EEPROM) chip.
Dedicated control circuitry non-volatile latch circuits are used in applications where only several bits (e.g., less than 32 bits) of data need to be stored. These non-volatile latch circuits each include their own dedicated control circuitry. A drawback with this type of latch circuit is that the dedicated control circuitry is complex and consumes a relatively large amount of chip area/volume since it requires numerous transistors to implement. For example, a conventional non-volatile latch circuit of this type may include 2 storage circuit transistors and 36 control circuit transistors. Thus the overwhelming majority of the transistors used in the non-volatile latch circuit are used for the dedicated control circuitry.
Accordingly, what is needed is a non-volatile latch circuit that has minimal control circuitry and thus consumes less chip area/volume on an integrated circuit device.
SUMMARY OF THE INVENTION
The present invention provides a non-volatile latch circuit and a corresponding method that has minimal control circuitry. The non-volatile latch circuit is typically used in applications where only several bits of data (e.g., less than 32 bits) need to be stored in non-volatile memory. The non-volatile latch circuit can be programmed and read using three control signals: a programming voltage/supply voltage signal, a data in signal, and a read/{overscore (write)} signal. By using fewer control signals, the number of transistors within the non-volatile latch circuit is reduced and thus the non-volatile latch circuit consumes less chip area/volume on an integrated circuit device.
In one embodiment of the present invention, a non-volatile latch circuit is disclosed. The non-volatile latch circuit includes a storage circuit, and a control circuit coupled to the storage circuit, the control circuit operable to program a logic value into the storage circuit using only a programming voltage/supply voltage signal, a data input signal, and a read/{overscore (write)} signal.
In another embodiment of the present invention, a non-volatile latch circuit is disclosed. The non-volatile latch circuit includes a storage circuit comprising a first floating gate transistor and a second floating gate transistor, and a control circuit. The control circuit includes a third transistor coupled to receive a programming voltage/supply voltage signal and a fourth transistor coupled to receive the programming voltage/supply voltage signal, a fifth transistor coupled to receive a data input signal and a first inverter coupled to receive the data input signal, and a second inverter coupled to receive a read/{overscore (write)} signal, a sixth transistor coupled to receive the read/{overscore (write)} signal, and a seventh transistor coupled to receive the read/{overscore (write)} signal.
In another embodiment of the present invention, a method for programming a non-volatile latch circuit is disclosed. The method includes increasing a programming voltage/supply voltage signal from a first voltage value to a second voltage value, maintaining the programming voltage/supply voltage signal at the second voltage value while maintaining a data input signal at a constant voltage value and while maintaining a read/{overscore (write)} signal at a constant voltage value, and decreasing the programming voltage/supply voltage signal from the second voltage value to the first voltage value.


REFERENCES:
patent: 5168464 (1992-12-01), Stanchak et al.
patent: 5587603 (1996-12-01), Kowshik
patent: 6307773 (2001-10-01), Smith
Betty Prince, “Semiconductor Memories”, 1983, Wiley, 2ndedition, pp. 152-154.

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