Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-11-14
2002-06-25
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S156000
Reexamination Certificate
active
06411545
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices. In particular, the present invention relates to a non-volatile latch.
2. The Prior Art
Rewritable, nonvolatile latches are useful for storing small amounts of data which should be stored when the power is disconnected from the circuit and then easily accessed without the necessity of employing sense amplifiers and, often, addressing circuitry. Examples of these applications are trimming of analog circuits, circuit ID information, or storage of addresses in redundancy repair. Because of the utility of a rewritable, nonvolatile latch, there have been a number of these devices developed over the years.
For example, a nonvolatile latch is disclosed in U.S. Pat. No. 4,113,904 to Harari. The latch of Harari has the drawback that the data read back is the complement of the data written into the cell. A noninverting latch circuit to overcome this drawback was disclosed in U.S. Pat. No. 4,348,745 to Schmitz. The Schmitz design has the drawback that it requires 12 transistors. Schmitz also suggests the application of 17 V for the write operation.
A rewritable, nonvolatile CMOS latch that can be fabricated with a single layer of polysilicon is disclosed in U.S. Pat. No. 4,858,185 to Kowshik and Lucero. The latch of Kowshik and Lucero requires only six transistors, two tunnel oxide capacitors, and two coupling capacitors. The process for fabricating the Kowshik and Lucero device requires the formation of separate buried n+ regions in addition to the thin tunnel oxide regions.
Yet another latch is disclosed in U.S. Pat. No. 5,097,449 to Cuevas. The Cuevas disclosure contains the provision that the data is stored on redundant nonvolatile memory elements for added reliability. Achieving this improvement in reliability requires the use of 10 transistors and 2 tunneling capacitors as well as the buried n+ regions used by Kowshik and Lucero.
A rewritable, nonvolatile latch that is programmed by electrons generated by band-to-band tunneling and cleared by tunneling from the floating gate to the well is disclosed in U.S. Pat. No. 5,781,471 to Kowshik and Yu. The Kowshik and Yu cell requires only six transistors in the latch, but requires both positive and negative high voltage for writing and also requires a separate clear operation before the data can be entered into the memory.
Rewritable, nonvolatile latches are typically employed in applications in which only a small amount of nonvolatile memory is in conjunction with other circuitry. In these applications, it is important that the nonvolatile latch requires as few additional process steps as possible and that the peripheral circuitry required to write to and read from the latch be as simple as possible so as to minimize the cost of the nonvolatile latch. Hence, there exists a need for a simple nonvolatile latch that requires a small number of transistors and a minimum number of extra process steps, and that can be written into a new state by applying a modest unipolar voltage to the latch.
BRIEF DESCRIPTION OF THE INVENTION
A non-volatile latch according to the present invention employs a pair of transistors, each with a floating gate that is capacitively coupled to the source of the paired transistor. The drains of the floating gate transistors are connected to the drains of another pair of transistors of opposite channel type; the gates of the second pair of transistors are cross coupled to the drains of the opposing members of the pair. A third pair of transistors is arranged so that one member of the pair is in series with the channels of the each of the sets of series connected n-channel and p-channel transistors. The gates of the third pair of transistors is biased so that current is blocked from flowing through the transistor channel during write and is allowed to flow through the channels during the read operation.
Data is written into the latch by applying a moderate high voltage to the source and well of one of the pair of floating gate transistors while the source and well of the other member of the pair is biased at ground. This bias causes electrons to tunnel from the floating gate to the channel region on one of the pair and from the channel region to the floating gate on the other of the pair; this current flow leaves one of the floating gates charged positive and the other charged negative.
The sources and wells of the floating gate transistors are biased at the same potential during read. As bias is applied across the CMOS inverters formed by the series connected n-channel and p-channel transistors, one floating gate transistor begins to conduct before the other with the result that the cross coupled inverters latch into a state in which one inverter is set high and the other is set low.
The result is that this configuration forms a latch that consumes only leakage current in both read and write modes. Because of the symmetry, a single write bias condition is sufficient to charge one floating gate while discharging the other.
Other objects, features and advantages of the present invention will be understood and appreciated be reference to the detailed descriptions provided below which should be considered in conjunction with the accompanying drawings.
REFERENCES:
patent: 4348745 (1982-09-01), Schmitz
patent: 5648930 (1997-07-01), Randazzo
patent: 5986932 (1999-11-01), Ratnakumar et al.
John Millard and Pamela Ann Caywood 1989 Revokable Living Trust
Le Vu A.
Sierra Patent Group Ltd.
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