Non-volatile large capacity high speed memory with electron inje

Details Non-volatile large capacity high speed memory with electron inje Non-volatile large capacity high speed memory with electron inje

1993-06-18

1995-02-28

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

257315, 257318, 257316, G11C 1140

Patent

active

053943600

ABSTRACT:
A non-volatile semiconductor memory providing a semiconductor substrate, drain and source regions which are provided on the surface of the semiconductor substrate and have a conductivity type different from that of the semiconductor substrate, a channel region formed between the drain and source regions, a floating gate (first gate electrode) for covering a part of the channel region. The drain region is self-aligned with the floating gate, and the source region is offset from the floating gate through an offset region by a constant distance. As a result, the drain and source regions are located asymmetrically with respect to the floating gate. A control gate (second gate electrode) substantially controls the surface potentials on the underside and in the vicinity of the floating gate. A selection gate (third gate electrode) controls the surface potential of the whole channel region including the offset region. The control gate as the second gate electrode is directly capacitively-coupled with the floating gate wholly (or partially) in portions other than the offset region. The selection gate is the third gate electrode is provided above the control gate and the floating gate so as to overlap with the control gate over all of the channel region, whereby electrons are injected from the source region to permit electrical writing and erasure.

REFERENCES:
patent: 4943836 (1990-07-01), Mori
patent: 5033023 (1991-07-01), Hsia et al.
patent: 5053841 (1991-10-01), Miyakawa et al.
patent: 5153691 (1992-10-01), Guterman
patent: 5231299 (1993-07-01), Ning et al.
patent: 5280446 (1994-01-01), Ma et al.
Kupec et al., "Triple Level Poly Silicon E.sup.2 PROM with Single Transistor per bit" IEEE IEDM 1980, pp. 602-606.

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