Static information storage and retrieval – Addressing – Multiplexing
Reexamination Certificate
1999-09-09
2001-01-23
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Multiplexing
C365S185110
Reexamination Certificate
active
06178132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile memory devices, such as flash memory based on floating gate memory transistors; and more particularly to processes for reading data from a non-volatile memory device while writing data to the same device.
2. Description of Related Art
One class of non-volatile memory device is referred to as flash memory. Flash memory is electrically erasable and programmable. The erase process in flash memory is applied to large blocks of cells at the same time, and has been called flash erase. Flash memory devices are typically manufactured using floating gate transistors, in which the erase process requires a significant amount of time to execute. By erasing a large block of memory cells at the same time, significant speed improvement is provided over other types of non-volatile memory devices using floating gate transistors. Also, the process of programming data in flash memory devices is a relatively time-consuming process.
One disadvantage of traditional flash memory arises from the relatively time-consuming processes of erasing and programming the devices. While these processes are being executed at one addressed location on the device, the rest of the memory cannot be used. The host processor is often idle while the flash memory is being programmed or erased.
Technology has developed to allow reading data from one set of memory cells on an integrated circuit while erasing or programming another set of memory cells. This prior art is represented by U.S. Pat. No. 5,245,572, entitled FLOATING GATE NON-VOLATILE MEMORY WITH READING WHILE WRITING CAPABILITY. Read while write capability allows the host processor to use the memory device for specific kinds of access, even while programming or erasing operations are occurring.
The prior art approaches require two separate memory arrays, having independent address decoders. In addition, the prior art approaches require separate address registers connected to the address inputs on the device, for the respective address decoders. Having the parallel address registers, address decoders, memory array structures allows the control logic on the chip to execute one process on one of the parallel arrays, while allowing the reading data from another of the parallel arrays. However, this duplicity comes at the cost of additional area and complexity on the integrated circuit, and consequently additional cost in manufacturing.
Therefore, it is desirable to provide non-volatile memory integrated circuit which is capable of reading while writing, which has a more efficient implementation, and which consumes less area on the integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides a more efficient read while write implementation and process for non-volatile integrate circuits. In particular, a non-volatile integrated circuit memory, such as a flash memory device based on floating gate transistor memory cells, with read while write capability is provided using a single address register. The integrated circuit includes at least two independent arrays of memory cells. During a program or an erase operation in one array on the non-volatile integrated circuit, a read operation can be executed in the other array on the same integrated circuit by bypassing the address register altogether, and allowing the register to remain in use by the program or erase operation. A bypass combinatorial logic path for the read process is coupled to the same address inputs as the address register, and is operable in parallel with the registered address path.
In one aspect of the invention, a non-volatile memory device is provided that comprises an integrated circuit substrate having a plurality of arrays of memory cells, including a first array of memory cells having a first address extent and a second array of memory cells having a second address extent. First and second address decoders are coupled to the first and second arrays, respectively. Control logic and bias resources on the integrated circuit substrate are coupled to the first and second memory arrays, and execute program and erase operations in response to commands on one of the first and second arrays, and execute read operations on the other of the first and second arrays during the execution of the program and erase operations. The integrated circuit substrate includes a set of address inputs and an address register. Selector circuitry responsive to the control logic operates to connect the set of address inputs to a first selected target selected from the address register, the first address decoder and the second address decoder. The selector circuitry also operates to connect the address register to a second selected target selected from the first address decoder and the second address decoder. During a program or erase operation, the address register is connected to the address decoder of the array being program or erased. The address inputs are isolated from the address register, and connected to the other address decoder coupled to the other array. When an address is received identifying the other array for a read, then the read is executed. This structure may be extended to provide for read while write capability with any number of independently addressable arrays on the integrated circuit.
According to one aspect of the invention, an address counter is included on the integrated circuit substrate, and connected with the address register. The address counter is controlled by the control logic during the erase or program operation, and applies addresses to the address register in support of such operations.
In another aspect, the integrated circuit substrate includes command decoder logic, which is coupled to the address register. Commands identifying the erase and program operations in this aspect of the invention include address sequences, which are supplied from the address register to the command decoder logic. The read process is executed without an address sequence based command. Rather, in one embodiment, the read process occurs whenever an address is received identifying a memory location in the array that is not subject to the erase or program operation, optionally in combination with enable signals which are independent of the address path.
The selector circuit in one embodiment includes an address input switch. The address input switch has a control input coupled to the control logic. An address input on the address input switch is coupled to the set of address inputs on the integrated circuit. An output of the address input switch is coupled to the address register. The address input switch either connects the address inputs to the address register or disconnects the address inputs from the address register in response to the control signal.
The selector circuit also includes first and second multiplexers. The multiplexers have respective control inputs connected to the control logic, address inputs coupled to the set of address inputs and to the address register, and an output connected to the respective one of the first and second address decoders. The multiplexers operate to connect either the address register or the address inputs to the respective address decoders in response to the respective control inputs.
In one embodiment, the address input switch comprises for each address input in the set, a logic gate having a first input coupled to an enable signal and a second input coupled to an address input, and a pass gate having an input coupled to the output of the logic gate and an output coupled to the address register. The pass gate is responsive to the signal on the switch control input to connect the output of the pass gate to the address register or to disconnect the output of the logic gate from the address register.
In one embodiment, each of the multiplexers is implemented with first and second pass gates. The input of the first pass gate is connected to the address input, such as at the output of the logic gate referred to above. The second pass gate has its input connec
Chen Han Sung
Hung Chun Hsiung
Liao Kuo Yu
Wan Ray Lin
Elms Richard
Haynes Mark A.
Haynes & Beffel LLP
Macronix International Co. Ltd.
Phung Anh
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