Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-02-18
2001-04-24
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185010, C365S185100, C365S185070
Reexamination Certificate
active
06222765
ABSTRACT:
TECHNICAL FIELD
The present invention relates to non-volatile memory cells connected in tandem to a volatile flip-flop, and more particularly to such a combination circuit whereby data contents of the volatile flip-flop can be stored in the non-volatile memory cells and vise versa.
BACKGROUND OF THE INVENTION
Volatile memories, such as static RAM latches are well known in the art. They are characterized by their ability to store and read out very quickly the data content stored therein. However, a drawback of volatile memory cell, such as a SRAM, is that the data content is lost once power is turned off.
Non-volatile memory cells, such as those using a floating gate to store electrical charges thereon, is also well known in the art. Their advantage is that the data content is stored even if power is turned off. However, the storing of even a single bit of information in a non-volatile memory cell is much slower than the storing of the bit information in a volatile memory cell.
Heretofore, the use of a combination of an SRAM with non-volatile memory cells is also well known in the art. Referring to
FIG. 1
, there is shown one embodiment of a combination circuit
10
. The circuit
10
comprises a conventional SRAM
20
. The SRAM
20
is characterized by a pair of cross-coupled PMOS transistors
22
and
24
, and a pair of cross-coupled NMOS transistors
26
and
28
. At a first node
30
, the input/output signal to and from the SRAM
20
can be provided. At the second node
32
, the inverse of the signal provided at the first node
30
can be provided to or from the SRAM
20
. Thus, as shown in
FIG. 1
, conventionally, the signal line BL is shown as being supplied to the first node
30
and its inverse {overscore (BL)} is supplied to the second node
32
. Each of the signals BL and {overscore (BL)} are supplied through respective switching transistors
34
and
36
whose gates are connected to the signal EERCL and which when activated serves to pass through the signal BL or {overscore (BL)} to or from the SRAM
20
.
The non-volatile memory cell section of the circuit
10
comprises a pair of split gate floating gate memory cells
40
and
42
of the type that is described in U.S. Pat. Nos. 5,029,130 and 5,572,054, whose disclosures are incorporated herein in their entirety by reference. As disclosed in these patents, each of the memory cells
40
and
42
comprises a first terminal and second terminal with a channel therebetween. A floating gate (shown as
44
and
46
, respectively for the cells
40
and
42
) is formed over a portion of the channel and is insulated therefrom and is over a portion of the first terminal. The first terminals of memory cells
40
and
42
are connected to MOS transistors
48
and
50
respectively, which are in turn connected to the switching transistors
34
and
36
. The gates of the transistors
48
and
50
are connected to the floating gates
44
and
46
respectively. Finally, the memory cells
40
and
42
further comprises control gates
52
and
54
respectively which overlap a portion of the channel. The control gates are connected together and receive the signal RCL. The second terminal of the memory cells
40
and
42
receive the signals BL and {overscore (BL)} respectively.
In the operation of the circuit
10
, the memory cells
40
and
42
are initially erased. As disclosed in U.S. Pat. Nos. 5,029,130 and 5,572,054, this means electrons are removed from the floating gates
44
and
46
respectively by tunneling electrons through an insulating layer to the control gates
52
and
54
respectively. This can be done, for example, by connecting the signal SL to ground, which connects the first terminals of the memory cells
40
and
42
to ground. The signal RCL is then connected to a source of high voltage such as +12 volts. This attracts the electrons on the floating gates
44
and
46
and causes them to tunnel through the insulating layer to the control gates
52
and
54
, to be removed from the floating gates
44
and
46
. The removal of the electrons from the floating gates
44
and
46
continues until the transistors
48
and
50
become conductive. This can be done by erasing the floating gates
44
and
46
so that the floating gates become positively charged.
Thereafter, one of the memory cells
40
or
42
is programmed. This can be accomplished by connecting the SL signal to +10 volts. WL is then connected to +1.8 volts. If memory cell
40
is to be programmed, then BL is connected to ground (or slightly above ground, such as 0.6 v) with {overscore (BL)} connected to Vcc. Since the voltage on {overscore (BL)} is higher than the voltage on WL, no electrons would flow in the channel between {overscore (BL)} and SL. However, since BL is at ground (or 0.6 v), its electrons would flow from BL to SL and would be hot channel injected onto the floating gate
44
, all as described in U.S. Pat. Nos. 5,029,130 and 5,572,054.
Once one of the memory cells
40
or
42
is programmed, then the state of the memory cells
40
and
42
can be written into the SRAM
20
. This can be accomplished by connecting EERCL to Vcc volts thereby turning on the pass transistors
34
and
36
respectively. SL is then connected to
0
.
0
volts. If the memory cell
40
is programmed, then electrons on the floating gate
44
cause transistor
48
to block the signal from SL to pass through transistor
34
to the first node
30
. However, for the memory cell
42
, since the floating gate is erased, transistor
50
would conduct and therefore the voltage from SL is passed through the transistor
50
and through the pass transistor
36
to second node
32
. Thus, the second node
32
is pulled down and the first node
30
is pulled up to Vcc, thereby programming the SRAM
20
.
There are many drawbacks of the circuit
10
. In particular, the circuit
10
does not permit the contents of the SRAM
20
to be written first and then written into the non-volatile memory cell. This leaves the disadvantage that programming has to occur always first into and from the non-volatile memory cells, which is time consuming.
SUMMARY OF THE INVENTION
Accordingly, in the present invention, a non-volatile flip-flop cell comprises a volatile flip-flop having a bit signal and an inverse bit signal. A first and second non-volatile cells are also provided with each cell having a first terminal and a second terminal with a channel therebetween. A floating gate is over a first portion of a channel and is over a portion of the second terminal and a control gate is over a second portion of the channel. A first switch supplies the bit signal to the first terminal of the first cell and the inverse bit signal to the first terminal of the second cell. A second switch supplies the bit signal to the first terminal of the second cell and the inverse bit signal to the first terminal of the first cell. A first means supplies a first voltage to the second terminal of the first and second cells and a second means supplies a second voltage to the control gate of the first and second cells.
REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5572054 (1996-11-01), Wang et al.
patent: 5625211 (1997-04-01), Kowshik
patent: 5644529 (1997-07-01), Pascucci et al.
patent: 5696455 (1997-12-01), Madurawe
patent: 5781471 (1998-07-01), Kowshik et al.
patent: 5812458 (1998-09-01), Gotou
patent: 5818753 (1998-10-01), Gotou
patent: 5978262 (1999-11-01), Marqust et al.
patent: 6067253 (2000-05-01), Gotou
patent: 6081575 (2000-06-01), Chevallier
patent: 6141247 (2000-10-01), Roohparvar et al.
See FIG. 1 of the drawings, further described in the specification of this application.
Gray Cary Ware & Freidenrich LLP
Nguyen Viet Q.
Silicon Storage Technology, Inc.
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