Non-volatile flash memory

Details Non-volatile flash memory Non-volatile flash memory

2005-07-05

2005-07-05

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185160

Reexamination Certificate

active

06914819

ABSTRACT:
A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.

REFERENCES:
patent: 5768192 (1998-06-01), Eitan
patent: 6687154 (2004-02-01), Lee et al.
C.C. Yeh et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory”, IEDM, 2000, pp. 931-934.
Amy Hsiu-Fen Chou et al., “Comprehensive Study on a Novel Bidirectional Tunneling Program/Erase NOR-Type (BiNOR) 3-D Flash Memory Cell”, IEEE Transactions on Electron Devices, vol. 48, No. 7, Jul. 2001, pp. 1386-1393.

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