Non-volatile eprom with increased efficiency

Static information storage and retrieval – Floating gate – Particular biasing

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357 23, G11C 1140

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active

043285651

ABSTRACT:
The floating gate in an N channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the channel and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain. A cell is erased either by ultraviolet illumination or by electrons from the floating gate tunneling through a region of thinned oxide. The non-symmetrical arrangement of the control gate and floating gate with respect to source and drain allows a very dense array implementation.

REFERENCES:
patent: 4087795 (1978-05-01), Rossler
patent: 4247916 (1981-01-01), Erb
Moller et al., "Programmable Read-Only-Memories", Conference, ISSCC 77, pp. 188-189, S7466 00014, Feb. 16-18, 1977.
Rossler, "Electrically Erasable and Reprogrammable Read-Only Memory Using the N-Channel SIMOS One-Transistor Cell," IEEE Trans. on Electron Devices, vol. ED-24, No. 5, 5/77, pp. 606-610.

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