Non-volatile electrically erasable memory with PMOS transistor N

Details Non-volatile electrically erasable memory with PMOS transistor N Non-volatile electrically erasable memory with PMOS transistor N

1995-11-14

1996-12-03

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular connection

36518528, 36518529, 365218, G11C 1140

Patent

active

055815049

ABSTRACT:
A NAND Flash EEPROM string is formed in a common N-well and includes a plurality of P-channel MOS stacked-gate storage transistors and P-channel MOS string and ground select transistors. In the preferred embodiment, each P-channel storage transistor is programmed via hot electron injection from the depletion region proximate its P+ drain/N-well junction and erased via electron tunneling from its floating gate to its P-type channel as well as to its P+ source and P+ drain regions without requiring high programming and erasing voltages, respectively. Further, high P/N junction biases are not required during programming or erasing operations. This allows the dimensions of the present embodiments to be reduced to a size smaller than that of comparable conventional N-channel NAND Flash EEPROM strings.

REFERENCES:
patent: 4435790 (1984-03-01), Tickle et al.
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patent: 5402373 (1995-03-01), Aritome et al.
patent: 5408431 (1995-04-01), Challa
Masanori Kikuchi, Shuichi Ohya and Machio Yamagishi, A New Technique To Minimize The EPROM Cell, IC Division, Nippon Electric Company, Ltd., 1753, Shimonumabe, Kawasaki, Japan, pp. 181-182.
Dov Frohman-Bentchkowsky, INTEL Corporation, Santa Clara, California, FAMOS-A New Semiconductor Charge Storage Device, Solid State Electronics 1974, vol. 17 pp. 517-529.
Constantine A. Neugebauer and James F. Burgess, General Electric Corporation, Session XV: Programmable Read-Only Memories, Feb. 18,1977, pp. 184 and 185.
S. Baba, A. Kita and J. Ueda, Mechanism of Hot Carrier Induced Degradation in MOSFET's, VLSI R&D Center, Oki Electric Industry Co., Ltd., 1986, pp. 734-737.

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