Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1999-12-21
2001-07-24
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S277000
Reexamination Certificate
active
06265924
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to tracking data using clock recovery modules in various data transmission applications such as transceivers using transmit and receive chips. More specifically, the present invention is directed to delay lines which operate over an increased frequency range in adjusting the effective delay in the clock path of a local clock.
2. Background
Clock recovery circuits track incoming data by properly aligning a local clock edge with the data transition edge. Alignment requires constant adjustment of the clock which is achieved by adding and reducing delay in the clock path. However, clock recovery architecture demands adherence to certain constraints which limit the operating frequency range of delay lines.
The first constraint is under a worst case (WC) process-voltage-temperature (PVT) condition occurring when the frequency of operation is at a maximum. A weak process, a low voltage and a high temperature make up a worst case condition which results in slow running logic. The delay of a single delay stage comprised of standard gates can vary as much as 2.5 times from one PVT extreme to another. For example, if the delay through one delay stage is 200 pico-seconds in the best case (BC) PVT condition, it would be 500 pico-seconds in the worst case PVT condition. The first constraint, (A), under the worst case condition demands that there be at least six elements or delay stages in the clock path in order to generate a delay of half a clock period at the maximum frequency of operation. In effect, the delay per stage should not exceed {fraction (1/12)}
th
of the clock period. The maximum frequency is thus represented by the following relationship:
Max. Frequency=1/[(# of delay stages)×(WC stage delay)×(2)] (A)
or
Max. Frequency=1/[(6)×(WC stage delay)×(2)]
Constraint (A) is necessary because when the delay through a single delay stage becomes a considerable portion of the clock period, the clock pulse will shrink so significantly when the delay stage is inserted or removed from the clock path that the clock pulse may eventually be completely lost at the end of the delay line. In addition, switching large single delay stages in and out of the clock path contributes to clock jitter.
The second constraint is under a best case (BC) PVT condition occurring when the frequency of operation is at a minimum. A best case condition results in fast running logic and arises from a strong process, a high voltage and a low temperature. The second constraint, (B), dictates that the delay line should generate a total delay of at least one half of the clock period in the best case condition at the minimum frequency. The minimum frequency is thus represented by the following relationship:
Min. Frequency=1/[(# of delay stages)×(BC stage delay)×(2)] (B)
Prior methods used in previous generations of products for adding and reducing delay in clock paths include the use of delay cells which are repeated several times to form a delay chain. The delay chain can be reconfigured to alter the path of the clock, thereby changing the amount of delay in the clock path. As illustrated by the four-stage delay line of
FIG. 1
, the clock path delay can be increased by shifting the four-bit digital select control, sel[
3
:
0
], from 0001 to 1000 and vice versa.
However, this and other prior methods have limited operating frequency ranges because they use identical delay stages in the delay chain. For example, where a single delay stage comprised of standard gates varies as much as 2.5 times from one PVT extreme to another, and the delay through a single delay stage is 200 pico-seconds in the best case and 500 pico-seconds in the worst case, the operating frequency range determined using the prior constraints (A) and (B) in a sixteen stage delay line is as follows:
Max. Frequency=1/[(6)×(500 ps)×(2)]=166 Mhz (A)
Min. Frequency=1/[(16)×(200 ps)×(2)]=156 Mhz (B)
This is a very narrow operating frequency range for the delay line, and increasing the range by extending the lower frequency margin would require adding more delay stages. This increases the necessary surface area and more importantly requires a redesign of the control logic controlling selection of the delay stages.
An alternative method for increasing the operating frequency range of delay lines involves the design of custom delay elements which have relatively small delay variation over PVT extremes. It is apparent from the maximum and minimum frequency equations for constraints (A) and (B) respectively, that a delay chain using identical elements designed in this manner would result in an increased operating frequency range for the delay line as the variation between the best case delay and the worst case delay would be minor. However, this method requires tightly controlled analog circuit design and results in a circuit which consumes more power.
Accordingly, there exists a need for an efficient, simple and inexpensive method for adding or reducing delay in a clock path.
SUMMARY OF THE INVENTION
A delay line provides a variable delay in the clock path and increases the operating frequency range through the use of delay stages which have non-uniform propagation delay with respect to one another. The range of operating frequency is increased by keeping the delay stages with the minimum propagation delay in the center of the delay line while the delay stages with the maximum propagation delay are toward the ends of the delay line.
REFERENCES:
patent: 5834960 (1998-11-01), Heima et al.
Le Dinh T.
LSI Logic Corporation
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