Non-stacked ECL type and function

Details Non-stacked ECL type and function Non-stacked ECL type and function

1987-05-28

1989-07-04

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307458, 307475, 307565, 357 15, H03K 19084

Patent

active

048453870

ABSTRACT:
A logic circuit which includes first and second differentially connected amplifying devices having first and second complementary output voltage nodes. Means for limiting the output voltage swing of the devices at the output nodes to a predetermined range reduces the required voltage supply source. A reference voltage is coupled to the second amplifying device while a plurality of input diodes are coupled in parallel to an input of the first amplifying device to form AND inputs thereto. A biasing element is coupled to the input of the first amplifying device.

REFERENCES:
patent: 4112314 (1978-09-01), Gani et al.
patent: 4518876 (1985-05-01), Constantinescu
patent: 4529894 (1985-07-01), Chan et al.
patent: 4575647 (1986-03-01), Ashton et al.
patent: 4636990 (1987-01-01), Buscaglia et al.
patent: 4680480 (1987-07-01), Hopta
patent: 4686395 (1987-08-01), Sato et al.
Chang et al., "Complementary Driver for Emitter-Coupled-Logic Gates", IBM T.D.B., vol. 19, No. 12, May 1977, pp. 4614-4615.

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