Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
1999-09-23
2001-05-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S309000, C438S341000
Reexamination Certificate
active
06228733
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of bipolar transistor manufacture with particular reference to formation of the base layer.
BACKGROUND OF THE INVENTION
It is common practice to form the base layer of a bipolar transistor through epitaxial deposition. This did not present serious problems in early devices but, as the sub-structure beneath the device has grown more complicated, and dimensional tolerances have narrowed, it has become necessary to develop methods for growing a base layer inside a small preset window and to then be able to make satisfactory contact to it. The selective epitaxial base bipolar transistor can allow the scaling of bipolar devices to less than that obtainable with conventional ion implantation techniques to produce a narrow base width in the deep submicron region.
A widely used approach to solving this problem has been selective epitaxial growth (SEG). SEG is a process that deposits single crystal Si layers only on the exposed Si substrate surface within the opening in the dielectric mask film, without the simultaneouds growth of Si in any form (polysilicon or amorphous) deposited on the silicon dioxide or silicon nitride layer. In the SEG process, SiCl
4
gas has frequently been used for the silicon source. The addition of HCl (or Cl
2
) to the reactive gas is believed to increase the selectivity of the growth process. Many factors may affect the selective nature of Si deposition, including the Si substrate surface condition, dielectric opening size, HCl concentration, silicon source, growth pressure and growth temperature. Many defects (e.g. microtwins, stacking faults and dislocations), can be observed at or near the epitaxi/dielectric interface.
The present invention teaches how non-selective deposition can be used to achieve the same end result as the prior art SEG process. The aforementioned crystal defects can be greatly reduced in the new process.
A routine search of the patent literature was performed but no references teaching the process of the present invention were encountered. Several references of interest were, however, identified. For example, Herbert et al. (U.S. Pat. No. 5,773,350) teach the formation of a base layer for a bipolar transistor through epitaxial growth but polysilicon contacts to said layer are formed separately and are not self aligned.
Sato (U.S. Pat. No. 5,599,723) grows his base layer through a mask using epitaxy. The mask opening is intentionally over-etched so as to produce an overhang at its edges. This eliminates any possibility of silicon deposited during the same step being used as a butted contact to the base layer.
Kimura et al. (U.S. Pat. No. 5,614,425) also deposits a silicon layer that is partly epitaxial (monocrystalline) and partly polycrystalline. They then mask the monocrystalline portion with insulation and proceed to use selective epitaxy in order to deposit additional silicon on the polycrystalline portion.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for manufacturing a bipolar transistor.
Another object of the invention has been that the base layer for said transistor be formed through non-selective epitaxial deposition.
A still further object has been that said base layer be contacted through self aligned butted contacts of polysilicon.
These objects have been achieved by first depositing a seed layer of polysilicon over both the field oxide and the wafer surface that lies between them. An opening in said seed layer is then formed between the areas of field oxide (and overlying an N+ buried subcollector). Non-selective epitaxial growth is then used to deposit the transistor's base layer. This automatically results in the formation of self aligned butted contacts of polysilicon on either side of the base. Manufacture of the transistor is completed in the usual way—emitter formation, emitter poly contact formation, ILD deposition, etc.
REFERENCES:
patent: 4824794 (1989-04-01), Tabata et al.
patent: 5073810 (1991-12-01), Owada et al.
patent: 5296391 (1994-03-01), Sato et al.
patent: 5323032 (1994-06-01), Sato et al.
patent: 5447885 (1995-09-01), Cho et al.
patent: 5599723 (1997-02-01), Sato
patent: 5614425 (1997-03-01), Kimura et al.
patent: 5773350 (1998-06-01), Herbert et al.
patent: 5877540 (1999-03-01), Naruse et al.
Huang Tzuen-Hsi
Lee Chwan-Ying
Ackerman Stephen B.
Industrial Technology Research Institute
Lattin Christopher
Niebling John F.
Saile George O.
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