Non-recovery parallel divider circuit

Details Non-recovery parallel divider circuit Non-recovery parallel divider circuit

1988-11-18

1991-04-09

Shaw, Dale M.

Boots, shoes, and leggings

G06F 752

Patent

active

050070096

ABSTRACT:
This invention provides a dividing circuit includes plural arithmetic units wherein the input on the numerator side is expressed as y.sub.s while the input on the denominator side is expressed as x.sub.s, and when the relationship (y.sub.s -x.sub.s).gtoreq.0 holds, each of the plural arithmetic units calculates the quotient as Z.sub.i with a remainder R.sub.s =y.sub.2 -x.sub.2 while when the relationship (y.sub.s -x.sub.s)<0 holds, it calculates the quotient Z.sub.i with a remainder R.sub.s =y.sub.s ; the dividing circuit inputs denominator side input x.sub.s at the arithmetic units, and inputs the numerator side input y.sub.s in the unit of bits corresponding to the arithmetic units together with remainder data from the higher order digit down, and then determines the whole of said bit quotient data from the arithmetic units as the quotient, and the remainder data of the least significant digit arithmetic unit as the remainder.

REFERENCES:
patent: 3257548 (1966-06-01), Fleisher et al.
patent: 3803393 (1974-04-01), Wang
patent: 4599702 (1986-07-01), Tokumitsu
patent: 4718031 (1988-01-01), Nukiyama

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