Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-05-06
1999-12-21
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438296, H01L 2176
Patent
active
060048638
ABSTRACT:
A non-polishing planarizing method for forming a planarized aperture fill layer within an aperture within a topographic substrate layer. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths, separated by a series of apertures. The series of mesas has formed thereupon a co-extensive series of patterned sacrificial layers. There is then formed upon the topographic substrate layer and the series of patterned sacrificial layers a blanket aperture fill layer employing a deposition and sputter method to fill the series of apertures to a planarizing thickness greater than the height of the mesas, while simultaneously forming a series of protrusions of the blanket aperture fill layer corresponding with the locations of the series of patterned sacrificial layers. There is then masked with a mask layer the blanket aperture fill layer to leave exposed at least a protrusion of the blanket aperture fill layer formed upon a widest of the patterned sacrificial layers. There is then etched while employing the mask layer and a first etch method at least a portion of the protrusion. There is then stripped from the microelectronics fabrication the mask layer. There is then etched while employing an isotropic second etch method which is selective to a remaining blanket aperture fill layer with respect to the patterned sacrificial layers the blanket aperture fill layer to form a series of patterned planarized aperture fill layers separated by the series of mesas, where the thickness of each patterned planarized aperture fill layer is substantially equivalent to the height of the mesas. Finally, there is stripped while employing an isotropic third etch method which is selective to the patterned sacrificial layers with respect to the patterned planarized aperture fill layers the patterned sacrificial layers from the topographic substrate layer to leave remaining the series of patterned planarized aperture fill layers substantially co-planar with the series of mesas which comprises the topographic substrate layer.
REFERENCES:
patent: 4954459 (1990-09-01), Avanzino et al.
patent: 4962064 (1990-10-01), Haskell et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5494854 (1996-02-01), Jain
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5665635 (1997-09-01), Kwon et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5851899 (1998-12-01), Weigand
patent: 5943590 (1999-08-01), Wang et al.
S. Nag et al. "Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub 0.25.mu.m Technologies", IEDM, '96, IEEE pp. 841-844.
Ackerman Stephen B.
Dang Trung
Saile George O.
Szecsy Alek P.
Taiwan Semiconductor Manufacturing Company
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