Non-PLL concurrent carrier clock synchronization

Details Non-PLL concurrent carrier clock synchronization Non-PLL concurrent carrier clock synchronization

1982-08-09

1984-09-18

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

375113, 329 50, 329100, H04L 2704

Patent

active

044728174

ABSTRACT:
Concurrent carrier and clock synchronization are derived from an input signal in interdependent loops without the use of phase look loop (PLL) circuitry in order to improve operation at higher bit rates. An acquisition detection signal is generated only in response to predetermined minimum errors in both the received signal amplitude and the recovered carrier phase.

REFERENCES:
patent: 3818347 (1974-06-01), Holsinger
patent: 3962637 (1976-06-01), Motley et al.
patent: 4004226 (1977-01-01), Qureshi et al.
patent: 4079329 (1978-03-01), England
patent: 4085378 (1978-04-01), Ryan et al.
patent: 4158105 (1979-06-01), Otani et al.
patent: 4215239 (1980-07-01), Gordy
patent: 4249252 (1981-02-01), Hofmeister
patent: 4295222 (1981-10-01), Van Uffelen
patent: 4344178 (1982-08-01), Waters
patent: 4384357 (1983-05-01), de Budda et al.

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