Non-overlapping clock phase splitter

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input

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327239, H03H 1122

Patent

active

058748458

ABSTRACT:
A circuit for splitting a clock signal to produce two clock signals of differing phases that do not overlap one another. The circuit includes a NFET, a first PFET, a second NFET and a second PFET. The drain terminals of the first NFET and first PFET are coupled to one another and provide a clock signal FCLKN. The source terminal of the first NFET is coupled to ground, and the source terminal of the first PFET is coupled to the power supply voltage VDD. Similarly, the drain terminals of the second NFET and second PFET are coupled to one another and provide a clock signal FCLK. The source terminal of the second NFET is coupled to ground, and the source terminal of the second PFET is coupled to VDD. The gate terminal of either the first NFET or the first PFET is coupled to a master clock signal. The gate terminal of the other is coupled to the drains of the second NFET and second PFET. Similarly, the gate terminal of the corresponding second NFET or PFET is coupled to the complement of the master clock signal. The gate terminal of the other is coupled to the drains of the first NFET and first PFET. FCLK does not overlap FCLKN because FCLKN cannot change state until FCLK has changed state, and vice versa.

REFERENCES:
patent: 4761568 (1988-08-01), Stronski
patent: 5047659 (1991-09-01), Ullrich
patent: 5306962 (1994-04-01), Lamb
patent: 5453707 (1995-09-01), Hiratsuka et al.
patent: 5495189 (1996-02-01), Choi
patent: 5672991 (1997-09-01), Thoma et al.
patent: 5751176 (1998-05-01), Sohn et al.
Non-Overlapping Clock Generator, IBM Technical Disclosure Bulletin, by Y. Hosoya and M. Kumagai, vol. 29, No. 1, Jun., 1986, pp. 263, 264.

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