Non-overlapping clock generator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307205, 307208, 307265, 328 62, 331 45, H03K 515, H03K 5153, H03B 2700, H03K 3353

Patent

active

041409272

ABSTRACT:
A two-phase, non-overlapping clock signal is generated in response to a single-phase input clock signal by delaying the input clock signal to produce the first phase output clock signal (.phi..sub.1), producing a delayed signal from the first phase clock signal, and gating the further delayed first phase clock signal with the input clock signal to produce an inverted signal for a second phase clock signal (.phi..sub.2), in order to produce gaps between the trailing edge of one phase of the output clock and the leading edge of the other phase of the output clock signal in order to accommodate dynamic transient conditions that must occur in a following utilization circuit between successive phase clock pulse signals.

REFERENCES:
patent: 3641370 (1972-02-01), Heimbigner
patent: 3740660 (1973-06-01), Davies, Jr.
patent: 3927334 (1975-12-01), Callahan
patent: 3946255 (1976-03-01), Stein
patent: 3950654 (1976-04-01), Broedner et al.
patent: 3961269 (1976-06-01), Alvarez, Jr.
patent: 3986046 (1976-10-01), Wunner
patent: 4034242 (1977-07-01), Heeren
patent: 4045685 (1977-08-01), Gehrig
Hatchett, "Nonoverlapping Clocks for Master-Slave Latch"; IBM Tech. Discl. Bull., vol. 19, No. 5, pp. 1695-1696, 10/1976.

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