Non-overlapping clock CMOS circuit with two threshold voltages

Details Non-overlapping clock CMOS circuit with two threshold voltages Non-overlapping clock CMOS circuit with two threshold voltages

1984-03-13

1986-06-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307452, 307481, 307360, 307579, 307264, 377 79, H03K 19096, H03K 1730

Patent

active

045958459

ABSTRACT:
A set of clock-controlled CMOS logic circuits employ a single pair of non-overlapping clocks controlling a set of transmission gates that have only a single pass transistor and a compensating non-standard threshold voltage in a portion of the logic gates.

REFERENCES:
patent: 3958187 (1976-05-01), Suzuki et al.
patent: 4250406 (1981-02-01), Alaspa
patent: 4390797 (1983-06-01), Ishimoto
patent: 4406957 (1983-09-01), Atherton
patent: 4446390 (1984-05-01), Alaspa
patent: 4463273 (1984-07-01), Dingwall
patent: 4485390 (1984-11-01), Jones et al.
patent: 4508983 (1985-04-01), Allgood et al.
Dennard, "Variation in Threshold Voltage Using Reduced Source-Drain Spacing", IBM Tech. Disc. Bull., vol. 12, No. 9, Feb. 1970, p. 1391.

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