Non-modulo power of 2 frequency divider

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377 47, G06F 752, H03K 2100

Patent

active

056338147

ABSTRACT:
A frequency divider/counter circuit utilizing at clock and a clear signal to divide the clock by an odd value. A first adder receives the clock and the clear signal, and has a carry-in input, and generates an adder output and carry-out output. A second adder also receives the clock and the first adder cell carry-out output, and generates an adder output. A reset cell receives the clock and the clear signal, and has an input and generates a reset output. Logic receives selected adder outputs and generates a divider output when the odd value is reached, wherein the first adder receives the divider output as its carry-in input, the second adder receives the carry-out output of the first adder as its carry-in input and the reset output as its clear input, and the reset cell receives the divider output as its input. The clear signal causes the frequency divider/counter to clear the outputs of the first and second adders, and, in the absence of the clear signal, generates a divider output when the adder outputs of the first and second adders represent the odd value upon which the adder output of the second adder clears. The frequency divider/counter circuit may also count an even value in which the carry-in input of the first adder is connected to ground, and, upon reaching the desired count, resets the outputs of both the first and second adders.

REFERENCES:
patent: 3230352 (1966-01-01), Grondin et al.
patent: 3873815 (1975-03-01), Summers
patent: 4078203 (1978-03-01), Borst
patent: 5390223 (1995-02-01), Lindholm

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