Non-linear phase detector

Details Non-linear phase detector Non-linear phase detector

2001-12-03

2003-09-02

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S025000, C327S009000, C327S012000, C327S156000, C327S159000

Reexamination Certificate

active

06614314

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the field of phase detectors. More particularly, a non-linear phase detector is provided that is especially well-suited for use in high-speed, high-performance clock and data recovery circuits.
BACKGROUND OF THE INVENTION
The use of a non-linear phase detector in a clock and data recovery circuit is known. For instance, a tri-state phase detector is shown in J. D. H. Alexander,
Clock Recovery from Random Binary Signals
, Electronic Letters, Vol. 11, October 1975, at 541. Known phase detectors, however, include many disadvantages that are overcome by the present invention.
Clock and data recovery circuits are typically implemented using a phase locked loop (PLL) that recovers a clock signal from a binary input signal by synchronizing a local clock signal with the rising and/or falling edges of the binary input signal.
FIG. 1
is a diagram of a typical phase locked loop
10
(PLL) configured as a clock and data recovery circuit. The PLL
10
includes a phase detector
12
, a charge pump
14
, a loop filter
16
and a voltage controlled oscillator
18
.
Operationally, the phase detector
12
receives an input data signal
22
, which is typically a binary NRZ (non-return to zero) data stream, and compares the rising and/or falling edges of the input data signal
22
with the rising and/or falling edges of a locally-generated (recovered) clock signal
20
in order to generate a phase detector output signal
26
. The phase detector output signal
26
typically indicates whether the rising and/or falling edges of the recovered clock signal
20
occur before (lagging clock) or after (leading clock) the rising and/or falling edges of the binary input data signal
22
. In addition, a typical phase detector
12
may also include a decision circuit (i.e. a retiming or reclocking flip-flop) which may utilize the recovered clock signal
20
to sample the input data signal
22
in order to reduce or remove random phase deviations (jitter) and generate a reclocked data signal output
24
. The phase detector output signal
26
is coupled to the charge pump
14
, which typically generates either a positive or negative output, depending upon whether the recovered clock signal
20
is leading or lagging. The charge pump output is then processed by the loop filter
16
and coupled to the voltage controlled oscillator
18
, which generates the recovered clock signal
20
that is fed back to the phase detector
12
.
SUMMARY
A non-linear phase detector includes a retiming stage and a phase synchronization stage. The retiming stage is coupled to a data signal and a recovered clock signal. The retiming stage is triggered by the recovered clock signal and samples the data signal to generate a retimed data signal and a clock synchronization signal. The phase synchronization stage is coupled to the retimed data signal and the clock synchronization signal. The phase synchronization stage is triggered by the retimed data signal and samples the clock synchronization signal to generate a phase control signal. This configuration optimizes the input jitter tolerance (IJT) of the retiming stage.


REFERENCES:
patent: 5126602 (1992-06-01), Lee et al.
patent: 5592125 (1997-01-01), Williams
patent: 5923190 (1999-07-01), Yamaguchi
patent: 6072336 (2000-06-01), Yamaguchi
patent: 92301224.9 (1992-08-01), None
Alexander, J.D.H., “Clock Recovery From Random Binary Signals”, Electronics Letters, vol. 11, pp. 242-243, Oct. 1975.
Greshishchev, Yuriy, Schvan, Peter, Showell, Jonathan, Xu, Mu-Liang, Ojha, Jugnu and Rogers, Jonathan, “A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate”, IEEE Journal of Solid State Circuits, vol. 35, No. 12, pp. 1949-1957, Dec. 2000.

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