Boots – shoes – and leggings
Patent
1995-08-28
2000-06-06
Ramirez, Ellis B.
Boots, shoes, and leggings
G06F 1700
Patent
active
060710047
ABSTRACT:
A structure and a format for providing a video signal encoder under the MPEG standard are provided. In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals. In one embodiment, the central processing unit (CPU) and multiple coprocessors implements DCT and IDCT and other signal processing functions, generating variable length codes, and provides motion estimation and memory management. The instruction set of the central processing unit provides numerous features in support for such features as alpha filtering, eliminating redundancies in video signals derived from motion pictures and scene analysis. In one embodiment, a matcher evaluates 16 absolute differences to evaluate a "patch" of eight motion vectors at a time.
REFERENCES:
patent: 3252148 (1966-05-01), Mitchell
patent: 3812467 (1974-05-01), Batcher
patent: 4489395 (1984-12-01), Sato
patent: 4514808 (1985-04-01), Murayama et al.
patent: 4559608 (1985-12-01), Young et al.
patent: 4591976 (1986-05-01), Webber et al.
patent: 4779190 (1988-10-01), O'Dell et al.
patent: 4783840 (1988-11-01), Song
patent: 4816914 (1989-03-01), Ericsson
patent: 4829380 (1989-05-01), Iadiapalo
patent: 4838685 (1989-06-01), Martinez et al.
patent: 4870563 (1989-09-01), Oguchi
patent: 4887306 (1989-12-01), Hwang et al.
patent: 4935942 (1990-06-01), Hwang et al.
patent: 4973860 (1990-11-01), Ludwig
patent: 5014187 (1991-05-01), Debize et al.
patent: 5040225 (1991-08-01), Gouge
patent: 5049993 (1991-09-01), LeGall et al.
patent: 5099322 (1992-03-01), Gove
patent: 5134480 (1992-07-01), Wang et al.
patent: 5144687 (1992-09-01), Honda
patent: 5157732 (1992-10-01), Ishii et al.
patent: 5157742 (1992-10-01), Niihara
patent: 5168356 (1992-12-01), Acampora et al.
patent: 5227878 (1993-07-01), Puri et al.
patent: 5231484 (1993-07-01), Gonzales et al.
patent: 5247586 (1993-09-01), Gobert et al.
patent: 5253078 (1993-10-01), Balkanski et al.
patent: 5270955 (1993-12-01), Bosshart et al.
patent: 5317397 (1994-05-01), Odaka et al.
patent: 5335321 (1994-08-01), Harney et al.
patent: 5400076 (1995-03-01), Iwamura
patent: 5408274 (1995-04-01), Chang et al.
patent: 5418907 (1995-05-01), Ohki
patent: 5438633 (1995-08-01), Ghaderi
patent: 5442747 (1995-08-01), Chan et al.
patent: 5455908 (1995-10-01), Ishida
patent: 5461423 (1995-10-01), Tsukagoshi
patent: 5475430 (1995-12-01), Hamada et al.
patent: 5486876 (1996-01-01), Lew et al.
patent: 5488419 (1996-01-01), Hui et al.
Gonzalez et al; "Image Processing" pp. 376-379 1987.
"A Complete Single-Chip Implementation of the JPEG Image Compression Standard", Martin Bolton, etc., IEEE Custom Integrated Circuits Conference, May 12-15, 1991, pp. 12.2.1-12.2.4.
"A Flexible Sampling-Rate Conversion Method", Julius O. Smith, etc., IEEE, 1984, pp. 19.4.1-19.4.4.
IEEE 1988 Custom Integrated Circuits Conference, May 1988 Rochester, N.Y., US, pp. 24.5.1-24.5.4, XP 000011005 Keshlear et al. A High Speed 16-Bit Cascadable Alu Using An Aspect Standard Cell Approaach.
IBM Technical Disclosure Bulletin, vol. 30, No. 11, Apr. 1988 New York US pp. 288-290, `Improved Zero Result Detection When Using a Carry Look-Ahead Adder`.
Patent Abstracts of Japan vol. 8 No. 248 (P-313), Nov. 14, 1984 & JP-A-59 121539 (Fujitsu Kabushiki Kaisha).
Xerox Disclosure Journal, vol. 13, No. 4, Aug. 1988 Stamford, Conn, US, pp. 229-234, XP 000098156, Marshall, `Fast NMOS Adder`.
Patterson, et al. `Computer Architecture A Quantitative Approach` 1990, Morgan Kaufmann, San Mateo, CA US, XP 000407059.
IBM Technical Disclosure Bulletin, vol. 25, No. 11A, Apr. 1983 New York US, pp. 5613-5620, `Phase Selector and Synchronizer for Two Phase Clock Circuits`.
IEEE Transactions on Circuits and Systems, vol. 36, No. 10, Oct. 1989 New York US, pp. 1275-1280, XP 000085314 Schmidt A Memory Control Chip for Formatting Data Into Blocks Suitable for Video Coding Applications p. 1277, right column, paragraph 2--p. 1278, left column, paragraph 3.
IEEE Transactions on Consumer Electronics, vol. 38, No. 3, Aug. 1992 New York US, pp. 325-340, XP 00011862 Netravali, et al. `A Codec for HDTV` *p. 327, left column, paragraph right column, paragraph 1*.
IEEE Journal of Solid-State Circuits, vol. SC-21, No. 1, Feb. 1986 New York US, pp. 140-149, Fortier et al. `Architectures for VLSI Implementation of Movement-Compensated Video Processors` *p. 142, left column, paragraph 3--right column, paragraph 1*.
Signal Processing Image Communication., vol. 3, No. 1, Feb. 1991 Amsterdam NL, pp. 3-21, XP 000234778 Fadzil, et al. `Video Subband VQ Coding At 64 kbit/s Using Short-Kernal Filter Banks With An Improved Motion Estimation Technique` *p. 7, left column, paragraph 1*.
IEEE Transactions on Communications, vol. COM-27, No. 9, Sep. 1979 New York, US, pp. 1310-1315, Wong, et al., `Hardwae for Detection and Partial Correction of PCM Transmission Errors` *p. 1311, left column, paragraph 6--right column, paragraph 1* *p. 1311, right column, last paragraph*.
Electronic Design, vol. 41, No. 9 May 1993 Hasbrouck Heights, New Jersey US, pp. 177-120, XP 000362680, Bursky, `Image Processing Chip Set Handles Full-Motion Video`.
Patent Abstracts of Japan vol. 13. No. 54 (p-824), Feb. 8, 1989 & JP-A-63 245716 (Fijitsu Limted) Oct. 12, 1988.
Le Gall Didier J.
Purcell Stephen C.
C-Cube Microsystems Inc.
Kwok Edward C.
Ramirez Ellis B.
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