Non-inverting three state TTL logic with improved switching from

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307456, 307458, 307443, H03K 19003, H03K 19084, H03K 19088, H03K 1716

Patent

active

047453087

ABSTRACT:
A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that eliminates a glitch in the output during the transition from the high impedance state to an active high. An output means includes a first transistor for supplying current to the output and a second transistor for draining current from the output. A phase splitting means determines the conductivity of the first and second transistors. A logic means is responsive to both an input signal and an output enable signal and is coupled to the phase splitting means. The logic means includes a level setting means that insures that the second transistor is not conductive during the transition of the output from the active high to the high impedance state.

REFERENCES:
patent: 3792292 (1974-02-01), Priel
patent: 3980898 (1976-09-01), Priel
patent: 4174541 (1979-11-01), Schmitz
patent: 4339676 (1982-07-01), Ramsey
patent: 4424455 (1984-01-01), Neely
patent: 4467223 (1984-08-01), Neely

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