Non-inverting high speed low level gate to Schottky transistor-t

Details Non-inverting high speed low level gate to Schottky transistor-t Non-inverting high speed low level gate to Schottky transistor-t

1984-08-27

1986-08-19

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 307473, 307475, 324 73R, 371 25, H03K 19088, H03K 19092, H03K 19003, G01R 3128

Patent

active

046071750

ABSTRACT:
A non-inverting high speed low level gate to Schottky transistor logic translator circuit includes a first input circuit adapted for receiving a first input signal and having its outputs connected to a first node and a second node. A first Schottky transistor is provided which has its base connected to the first node and to a voltage supply potential via a first resistor, its emitter connected to the second node and its collector connected to a third node and to the supply potential via a second resistor. A second Schottky transistor is provided which has its base coupled to the third node, its collector connected to the supply potential via a third resistor and its emitter connected to a fourth node. An upper output transistor has its base connected to the fourth node and to a ground potential via a fourth resistor, its collector connected to the supply potential via a fifth resistor and its emitter connected to an output circuit terminal. A lower output transistor has its base connected to the second node, its collector connected to the output circuit terminal and its emitter connected to the ground potential. Second and third circuits formed of low level NAND gates are adapted for receiving test input signals and have their outputs connected to the first and second nodes for testing purposes. A fourth input circuit formed of low level NAND gates is adapted for receiving a second input signal and has its outputs connected to the second node and the third node for turning off the lower output and upper output transistors so as to maintain the output circuit terminal in high impedance state.

REFERENCES:
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patent: 4042840 (1977-08-01), Chan
patent: 4255670 (1981-03-01), Griffith
patent: 4287433 (1981-09-01), Goodspeed
patent: 4486674 (1984-12-01), Neely
patent: 4527115 (1985-07-01), Mehrotra et al.
patent: 4536664 (1985-08-01), Martin
Culican et al, "Driver Circuit With Controlled Output Up-Level"; IBM TDB; vol. 26, No. 8, pp. 4059; 1/1984.

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