Non-inverting buffer circuit device and semiconductor memory cir

Details Non-inverting buffer circuit device and semiconductor memory cir Non-inverting buffer circuit device and semiconductor memory cir

1991-10-29

1994-04-19

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307570, 36523008, H03K 1902, G11C 800

Patent

active

053048687

ABSTRACT:
A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential. The inverted signal outputting circuit includes a bipolar transistor producing an output signal at its collector potential, a first switching circuit for controlling supply of a collector current to the bipolar transistor, an n-channel MOS transistor, connected in parallel between the base and the collector of the bipolar transistor, for supplying a base current to the bipolar transistor in accordance with the input signal, and a second switching circuit for controlling supply of the base current to the bipolar transistor, wherein the first switching circuit and the second switching circuit are selectively on-off controlled.

REFERENCES:
patent: 4558234 (1985-12-01), Suzuri et al.
patent: 4948994 (1990-08-01), Akioka et al.
patent: 5001366 (1991-03-01), Masuda et al.
patent: 5097150 (1992-03-01), Satou et al.

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