Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-10-19
2002-12-10
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090
Reexamination Certificate
active
06492827
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to an apparatus and method for measuring electrical properties of a semiconductor wafer.
2. Description of the Background Art
The determination of electrical properties of a dielectric on a semiconductor wafer and/or a carrier density profile within the semiconductor wafer is a critical factor in the production of such wafers. Measurements based on capacitance-voltage (CV) techniques, such as measurements of dielectric thickness, oxide charge, threshold voltage, implant dose and carrier profile, and measurements based on current-voltage (IV) techniques, such as dielectric leakage current and breakdown voltage, are typically accomplished by first fabricating metal or doped polysilicon gates on the dielectric. These gates become part of a metal oxide semiconductor (MOS) structure which is used to make the appropriate CV or IV measurement.
Fabrication of the metal or polysilicon gates is time-consuming and costly. It typically involves depositing and forming aluminum metal or polysilicon gates on the dielectric in a manner known in the art.
An alternative to these fabricated gates is described in an article entitled “Vacuum Operated Mercury Probe for CV Plotting and Profiling” by Albert Lederman, Solid State Technology, August 1981, pp. 123-126. This article discloses utilizing mercury contacts for replacing the aluminum or polysilicon gates in CV measurement techniques designed to characterize dielectric and semiconductor properties. The Lederman paper discloses a vacuum operated mercury probe for performing measurements of metal oxide semiconductors, homogeneous semiconductor wafers, non-homogeneous semiconductor wafers, and semiconductor wafers on insulating substrates. Problems may arise utilizing the Lederman mercury probe in that mercury may react chemically with the materials of the wafer under study. Mercury also poses a significant safety problem in its use and mercury sublimes at elevated temperatures when accelerated temperature testing of the semiconductor wafer is desired. Thus, a mercury probe has limited application.
An alternative to fabricated gates or vacuum operated mercury probes is disclosed in U.S. Pat. No. 5,023,561 to Hillard which issued on Jun. 11, 1991 and which is incorporated herein by reference.
The Hillard patent discloses a kinematic probe arm having at one end thereof a probe including a tip having a uniformly flat surface of predetermined dimensions. A probe stand supports the kinematic arm and a chuck supports the semiconductor wafer. The probe stand, the kinematic arm, and the chuck are configured so that a planar contact can be realized between the uniformly flat portion of the tip and the front surface of the dielectric layer of the semiconductor wafer.
When the Hillard patent was filed in the early 1990's, a typical gate oxide thickness in the semiconductor industry was on the order of hundreds of angstroms. The relatively small planar contact area between the uniformly flat tip of the probe and the outer surface of the dielectric layer on the wafer resulted in a poor capacitance signal-to-noise ratio when applied to these relatively thick oxides. Hence, while the probe having the uniformly flat tip could be utilized for performing CV measurements, this probe was preferably utilized to perform IV measurements.
In contrast, today, gate oxides are very thin, on the order of 3.5 nm. With these thin oxides, the capacitance signal-to-noise ratio is increased whereby CV measurements made with conductive pressure contacts can be effectively utilized to characterize gate oxides.
A problem with utilizing the probe disclosed in the Hillard patent for performing CV measurements is the need to grind the tip uniformly flat. Another problem is the need to establish a planar contact between the uniformly flat tip and the outer surface of the dielectric layer of the wafer. The use of a uniformly flat tip to form a planar contact within the outer surface of the dielectric layer is particularly a problem with today's thin oxide layers since a lack of perfect parallelism between the uniformly flat tip and the outer surface of the dielectric layer may result in an edge surrounding the uniformly flat tip damaging the oxide layer.
It is, therefore, an object of the present invention to avoid or overcome the above problems and others by providing a probe having an improved tip configuration that enables improved CV measurements of dielectric layers on a semiconductor wafer. Still other objects of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.
SUMMARY OF THE INVENTION
Accordingly, we have invented an apparatus for measuring at least one electrical property of a semiconductor wafer. The apparatus includes an assembly for supporting a semiconductor wafer and a probe having an elastically deformable conductive tip for contacting a front surface of the semiconductor wafer. The front surface of the semiconductor wafer can be (i) a dielectric formed on a front surface of semiconducting material which forms the semiconductor wafer or (ii) the semiconducting material. Also provided are an electrical contact for contacting the semiconductor wafer and a means for applying an electrical stimulus between the elastically deformable conductive tip and the electrical contact. A means is provided for measuring a response to the electrical stimulus and for determining from the response at least one electrical property of the dielectric and/or the semiconducting material.
The response to the electrical stimulus occurs at a boundary of the dielectric and the semiconducting material or in a region adjacent the front surface of the semiconducting material.
The dielectric includes at least one dielectric layer. The at least one dielectric layer can include a native dielectric layer which forms in response to exposure of the semiconducting material to air. Preferably, the conductive tip is formed from metal, such as tantalum, conductive elastomer, or conductive polymer.
A surface of the conductive tip for contacting the front surface of the semiconductor wafer has the form of a truncated sphere, e.g., a hemisphere, having a radius of curvature between 10 &mgr;m and 100 cm. When the conductive tip is in contact with the dielectric, an effective air gap is formed therebetween having an insulating value equivalent to an actual air gap of less than or equal to 1 nm, 0.8 nm, or 0.2 nm.
An electrically conductive sleeve can surround the probe and an insulator can be disposed between the probe and the sleeve. The sleeve can be connected to an electrical ground or can be connected to receive an electrical signal which biases the sleeve to the same potential as the conductive tip.
A kinematic probe arm assembly can be connected to the probe for controlling a force of the conductive tip on the front surface of the semiconductor wafer and the rate this force is applied to the front surface. The kinematic probe arm assembly can also avoid scrubbing of the elastically deformable conductive tip on the front surface of the semiconductor wafer when the tip moves into contact therewith.
We have also invented a semiconductor wafer probe assembly having a chuck assembly configured to receive a back surface of a semiconductor wafer and an electrical contact for contacting the semiconductor wafer. A probe is provided having an elastically deformable conductive tip which is movable into contact with (i) a front surface of a dielectric formed on a front surface of semiconducting material forming the semiconductor wafer or (ii) a front surface of the semiconducting material. A means is provided for applying an electrical stimulus between the electrical contact and the elastically deformable conductive tip, for measuring a response to the electrical stimulus, and for determining from the response at least one electrical property of the dielectric and/or the semiconducting material.
The electrical contact can contact
Hillard Robert J.
Mazur Robert G.
Nguyen Vinh P.
Solid State Measurements, Inc.
Webb Ziesenheim & Logsdon Orkin & Hanson, P.C.
LandOfFree
Non-invasive electrical measurement of semiconductor wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-invasive electrical measurement of semiconductor wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-invasive electrical measurement of semiconductor wafers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2974810