Non-intrusive performance monitoring

Details Non-intrusive performance monitoring Non-intrusive performance monitoring

1998-05-05

2001-08-14

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system

Performance or efficiency evaluation

C702S183000, C702S189000, C702S198000

Reexamination Certificate

active

06275782

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to performance monitoring in integrated circuits.
2. Description of the Related Art
Most microprocessors used in desk top computer systems, are equipped with performance monitoring counters. These counters permit processor performance parameters to be monitored and measured. Such information is useful for performance tuning. Current techniques typically utilize two counters which simultaneously record the occurrence of prespecified events. W hen one of the counters overflows, counting stops and an interrupt is generated. Post-processing software is use d to analyze the gathered data.
Typically two large counters, of e.g., 40-bits or more, are provided for event counting. The counters can generally be read and written from within register address space. The counters can be configured to measure such parameters as the number of data reads that hit in the cache. When configured to determined cache hits, the first counter is programmed to record the number of cache hits and the second counter is programmed to record the number of actual data reads performed. The ratio of the two numbers gives the cache hit rate for read operations. Measured performance parameters are a good estimate of future performance. Actual performance at any instant may vary widely from the measured estimate. The typical use of two large counters does not make any attempt to measured this deviation from the average.
When one of the counters reaches its limit, the overflow signal stops all counting and generates an interrupt. The software interrupt handler then records the counter values, completes post data processing and any other support work necessary.
The size of the counters is important. The larger the counter, the less frequently an interrupt is generated. Such interrupts are undesirable because they intrude into normal processor operation. A larger counter also results in greater data averaging. Therefore, temporary fluctuation in cache hit rate may not be observed. Such temporary fluctuations may, or may not be what is of interest.
Before performance monitoring can be accomplished, an interrupt handler must be installed to deal with counter overflow. Of course, overflow can be avoided by the use of extremely large counters. But extremely large counters may be expensive to implement, unreliable or fail to produce the desired analysis. It would be desirable to monitor performance parameters in an integrated circuit such as a processor without having to provide two large counters, without having to deal with counter overflow, without having to provide software interrupt handlers. It would also be desirable to avoid intrusion of the performance monitoring into the normal functioning of the processor in the system.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a new technique for gathering and analyzing performance data with a microprocessor or microcontroller or other integrated circuit. The technique avoids the limitations imposed by fixed size counters which eventually overflow. The method is less intrusive and suitable for monitoring a wide range of performance parameters.
In a first embodiment an integrated circuit includes a performance monitoring circuit which includes an adaptive adder circuit coupled to receive a first input signal indicative of a performance parameter of the integrated circuit and to provide a count value as a measure of the performance parameter. The adaptive adder circuit includes a random number generator circuit providing a random number, a counter circuit providing a count value and a comparator circuit coupled to compare the random number and the count value and to output a compare signal indicative thereof, the compare signal being provided to the counter as an up/down count signal. The adaptive adder circuit also includes a first logic circuit coupled to receive the performance parameter being measured and the compare signal. The first logic circuit outputs a first control signal which is used for controlling operation of the counter circuit. The counter circuit is responsive to count up or down when the first input signal and the compare signal are at different values and the counter circuit does not count when the first input signal and the compare signal are at the same value.
In another embodiment a method of measuring a performance parameter in an integrated circuit includes providing to an adaptive adder circuit, a first input signal indicative of the performance parameter and providing a count value in the adaptive adder circuit as a measure of the performance parameter. The method further includes generating a random number in a random number generator circuit, providing a counter circuit providing the count value, and comparing the random number and the count value and providing a compare signal. The compare signal is provided to the counter circuit as a first control signal. The method further includes logically combining the performance parameter and the compare signal to provide a second control signal for controlling operation of the counter circuit.


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