Non-integral delay circuit

Details Non-integral delay circuit Non-integral delay circuit

1993-05-13

1994-09-20

Mai, Tan V.

Boots, shoes, and leggings

36472401, G06F 1531

Patent

active

053495489

ABSTRACT:
A non-integral delay circuit for delaying a digital signal by a selectable fraction (.delta.) of a sampling period of the digital signal includes a first differentiator (S3) to obtain a first differential signal (F1) having a first phase characteristic with respect to the digital signal, a second differentiator (D) to obtain a second differential signal (F2) having a second phase characteristic with respect to the digital signal, the first and second phase characteristics differing from each other, a mixer (MIX) for combining the first (F1) and second (F2) differential signals in dependence on the selectable fraction (.delta.) to obtain a phase-adjusted correction signal, and an adder (A9) which adds a product (M3) of the selectable fraction (.delta.) and the phase-adjusted correction signal to the digital signal, to obtain the digital signal delayed by the selectable fraction (.delta.) of the sampling period of the digital signal.

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patent: 5257026 (1993-10-01), Thompson et al.
patent: 5258939 (1993-11-01), Johnstone et al.
M. Herrmann, "Digitaler Fernsehempfanger mit unverkoppeltem Systemtakt", Fernseh Und Kino Technik, vol. 44, No. 4, 1991, pp. 282-289.
P. Knutson et al., "An Optimal Approach To Digital Raster Mapper Design", IEEE Transactions on Consumer Electronics, vol. 37, No. 4, Nov. 1991, pp. 746-752.

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