Non-integer division of frequency

Details Non-integer division of frequency Non-integer division of frequency

2001-08-14

2003-08-26

Callahan, Timothy P. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C327S117000

Reexamination Certificate

active

06611573

ABSTRACT:

BACKGROUND OF THE INVENTION
As the operating frequencies of modern computers continue to increase, power consumption by such computers increases accordingly. The relationship between power consumption and frequency is given in Equation 1.
P=CV
2
f
  (1)
In Equation 1, P represents power, C represents capacitance, V represents voltage, and f represents frequency. It is evident from Equation 1 that as f increases, P increases proportionally.
However, sometimes, increased power consumption may not be desirable or feasible at all parts of a computer system due to one or more system constraints, testing purposes, or performance concerns. For example, when power consumption is increased, temperature accordingly increases, and this may lead to diminished reliability. Further, due to increased power consumption at certain parts of the computer system, the supply of power at other parts of the computer system may be adversely affected. Thus, in order to avoid such problems caused by increased power consumption, frequency at particular parts of the computer system is decreased, i.e., “divided down.”
FIGS. 1
a
and
1
b
show a typical prior art approach to dividing down a frequency of a signal.
Specifically,
FIG. 1
a
shows a frequency divider (
10
) that is formed by a positive edge-triggered D-Q flip-flop (also referred to as “D-Q flip-flop”) (
12
) and a delay stage (
14
), which is formed by an inverter (
16
). An input signal, CLK_IN, serves as an input to a clock input of the D-Q flip-flop (
12
). A Q output of the D-Q flip-flop (
12
), via FLIP_FLOP_OUT, serves as an input to the delay stage (
14
), which, in turn, outputs to both a D input of the D-Q flip-flop (
12
) and an output, CLK_OUT, of the frequency divider (
10
).
FIG. 1
b
shows a timing diagram (
20
) of the frequency divider (
10
) shown in
FIG. 1
a
. If the D input to the D-Q flip-flop (
12
) is initially logic high, i.e., ‘1’, when a first positive edge, i.e., a first “rising” edge, on CLK_IN (
22
) triggers the D-Q flip-flop (
12
), the D-Q flip-flop outputs logic high on FLIP_FLOP_OUT (
24
). The logic high on FLIP_FLOP_OUT (
24
) is inputted by the delay stage (
14
), which, in turn, inverts the logic high on FLIP_FLOP_OUT (
24
) and outputs logic low, i.e., ‘0’, on CLK_OUT (
26
). The logic low outputted by the delay stage (
14
) also propagates to the D input of the D-Q flip-flop (
12
) to ready the D-Q flip-flop (
12
) for the next time it is triggered.
A next rising edge on CLK_IN (
28
) triggers the D-Q flip-flop (
12
) causing the D-Q flip-flop (
12
) to output logic low on FLIP_FLOP_OUT (
30
) due to the logic low at the D input of the D-Q flip-flop (
12
). The logic low on FLIP_FLOP_OUT (
30
) is inputted by the delay stage (
14
), which, in turn, inverts the logic low on FLIP_FLOP_OUT (
30
) and outputs logic high on CLK_OUT (
32
). The logic high outputted by the delay stage (
14
) also propagates to the D input of the D-Q flip-flop (
12
) to ready the D-Q flip-flop (
12
) for the next time it is triggered.
The description of the timing diagram (
20
) of
FIG. 1
b
shows that the frequency of CLK_OUT is one-half that of CLK_IN. In other words, the frequency of CLK_OUT is equal to the frequency of CLK_IN divided by two. Essentially, the frequency divider (
10
) of
FIG. 1
a
and other prior art frequency dividers generate an output signal by counting the number of cycle of an input signal. For example, the frequency divider (
10
) of
FIG. 1
a
generates one cycle on an output signal for every two cycles on an input signal. Furthermore, the capability of most frequency dividers can be extended to allow the generation of multiple output signal frequencies, where the multiple output signal frequencies are generated by dividing down an input signal's frequency by particular integer values.
FIG. 2
a
shows a typical prior art frequency divider (
40
) that is capable of generating multiple output signal frequencies. Specifically,
FIG. 2
a
shows a frequency divider (
40
) that is formed by four negative edge-triggered J-K flip-flops (also individually referred to as “J-K flip-flop”) (
42
,
44
,
46
,
48
). The J and K inputs to the four J-K flip-flops (
42
,
44
,
46
,
48
) are tied to logic high, and thus, every time a negative edge, i.e., a “falling” edge, arrives at a clock input of one of the four J-K flip-flops (
42
,
44
,
46
,
48
), the value stored inside that J-K flip-flop is inverted. The Q outputs of the first, second, and third J-K flip-flops (
42
,
44
,
46
) are connected to the clock inputs of the second, third, and fourth J-K flip-flops (
44
,
46
,
48
), respectively. Further, the signals from the Q outputs of the first, second, and third J-K flip-flops (
42
,
44
,
46
) are represented by C
0
, C
1
, and C
2
, respectively. The clock input of the first J-K flip-flop (
42
) is connected to an input signal, CLK, and the signal from the Q output of the fourth J-K flip-flop (
48
) is represented by C
3
.
FIG. 2
b
shows a timing diagram (
50
) of the frequency divider (
40
) shown in
FIG. 2
a
. Initially, the four J-K flip-flops (
42
,
44
,
46
,
48
) store a logic low. At a first falling edge of CLK (
52
), the clock input of the first J-K flip-flop (
42
) is pulsed and the value stored in the first J-K flip-flop (
42
) goes from logic low to logic high, which results in logic high to go from the Q output of the first J-K flip-flop (
42
) to the clock input of the second J-K flip-flop (
44
). Moreover, this logic high at the Q output of the first J-K flip-flop (
42
) causes C
0
to go high (
54
). Thus, the first falling edge (
52
) at the clock input of the first J-K flip-flop (
42
) causes C
0
to go high (
54
). However, the logic high on C
0
(
54
) does not affect the value stored in the second J-K flip-flop (
44
) because the second J-K flip-flop (
44
) can only be triggered by a falling edge at its clock input.
At a second falling edge of CLK (
56
), the clock input of the first J-K flip-flop (
42
) is pulsed and the value stored in the first J-K flip-flop (
42
) goes from logic high to logic low, which results in logic low to go from the Q output of the first J-K flip-flop (
42
) to the clock input of the second J-K flip-flop (
44
). Moreover, this logic low at the Q output of the first J-K flip-flop (
42
) causes C
0
to go low (
58
) and triggers the second J-K flip-flop (
44
). Thus, because C
0
goes high (
54
) at a first falling edge of CLK (
52
) and C
0
goes low (
58
) at a second falling edge of CLK (
56
), C
O
's frequency is one-half of CLK's frequency. In other words, the frequency divider (
40
) can generate a signal that has a frequency equal to that of a clock signal's frequency divided by two.
Because the second J-K flip-flop (
44
) is triggered by the falling edge on C
0
(
58
), the value stored in the second J-K flip-flop (
44
) goes from logic low to logic high, which results in logic high to go from the Q output of the second J-K flip-flop (
44
) to the clock input of the third J-K flip-flop (
46
). Moreover, this logic high at the Q output of the second J-K flip-flop (
44
) causes C
1
to go high (
60
). Thus, the second falling edge (
56
) at the clock input of the first J-K flip-flop (
42
) causes C
0
to go low (
58
), which, in turn, triggers the second J-K flip-flop (
44
) and causes C
1
to go high (
60
). However, the rising edge on C
1
(
60
) does not affect the value stored in the third J-K flip-flop (
46
) because the third J-K flip-flop (
46
) can only be triggered by a falling edge at its clock input.
At a fourth falling edge of CLK (
62
), the clock input of the first J-K flip-flop (
42
) is pulsed and the value stored in the first J-K flip-flop (
42
) goes from logic high to logic low, which results in logic low to go from the Q output of the first J-K flip-flop (
42
) to the clock input of the second J-K flip-flop (
44
). Moreover, this logic low at the Q output of the first J-K flip-flop (
42
) causes C
0
to go low (
64
) and triggers the second J-K flip-flop (
44
).
Because the second J-K f

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