Non-fully-decoded test address generator

Details Non-fully-decoded test address generator Non-fully-decoded test address generator

1994-10-11

1995-05-30

Nguyen, Hoa

Excavating

G11C 2900

Patent

active

054208700

ABSTRACT:
An address count which increases up to, or decreases down from, a user-selected value is generated by a non-fully-decoded address generator (10) which is configured of a plurality of interconnected, sequentially-actuated of bit generators (12'.sub.1 -12'.sub.k), each generating a separate one of the bits of the address count. Each of the bit generators is presettable to at least one logic state, with at least one bit generator being presettable to a separate one of two logic states. A control circuit (30' presets the bit generators in accordance to the user-selected initial value so that when the bit generators are sequentially actuated, their collective count runs up to, or down from, the seed value.

REFERENCES:
patent: 4442519 (1984-04-01), Jones et al.
patent: 4872168 (1989-10-01), Aadsen et al.
patent: 5151903 (1992-09-01), Mydill et al.

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