Non-destructive sampling of internal states while operating at n

Details Non-destructive sampling of internal states while operating at n Non-destructive sampling of internal states while operating at n

1995-10-05

1996-06-25

Voeltz, Emanuel T.

Excavating

371 221, 371 222, 371 224, 371 225, 371 226, 307407, G06F 1520, H04B 1700

Patent

active

055307060

ABSTRACT:
A test system for a digital integrated circuit in which internal states of the integrated circuit are captured non-destructively while the digital circuit is operating at normal clock speed. Cells for capturing states are sequentially connected into shift registers. Once internal states are latched within cells, the captured states are serially shifted out a test port while the integrated circuit continues to operate. State sampling is triggered internally via a software command or externally via an external signal synchronized to an internal clock.

REFERENCES:
patent: 4597042 (1986-06-01), d'Angeac et al.
patent: 5231314 (1993-07-01), Andrews
patent: 5299136 (1994-03-01), Babakanian et al.
patent: 5313470 (1994-05-01), Simpson
Pereira et al., "Pipelined TSPC barrel shifter with scan test facilities for VLSI implementation of high speed DSP applications"; IEEE, 1992; Periodical: EURO ASIC pp. 405-466.
Josephson et al., "Test Features of HP PA7100LC processor"; IEEE conference paper; 17-21 Oct., 1993 pp. 764-772.

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