Non-contiguous memory location addressing scheme

Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit

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Details

711217, 711173, 36523001, 36523003, 36523006, G06F 1206

Patent

active

057741352

ABSTRACT:
A processing system and method is disclosed to access non-contiguous memory locations within a memory block. An address is generated that has a first group of bits and a second group of bits. The first group is decoded to select one of a number of memory blocks. The second group has n bits configured to select any one of (2.sup.n -(n+1)) unique combinations of the locations within the selected block. This second group provides a different pattern corresponding to each different combination of the locations within the selected block. An application of this addressing scheme for video graphics processing is also disclosed.

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