Boots – shoes – and leggings
Patent
1993-11-12
1996-08-20
Teska, Kevin J.
Boots, shoes, and leggings
395412, 395416, 395442, 395418, 395700, 395490, 364DIG1, 364DIG2, 380 4, 380 49, G06F 300, G06F 926
Patent
active
055487467
ABSTRACT:
A system and method for protecting individual segments of a contiguous I/O address space on a system bus using the page access protection resources of a processor operating on a processor bus address space. The contiguous I/O address space is segmented and mapped by translation into the processor address space by distributing I/O segments non-contiguously among successive processor bus pages. Individual I/O address space segments, as may be associated with I/O ports, are protected directly by the processor through the selective enablement of page protection for correspondingly mapped ports.
REFERENCES:
patent: 4035779 (1977-07-01), Birney et al.
patent: 4037207 (1977-07-01), Birney et al.
patent: 4037214 (1977-07-01), Birney et al.
patent: 4037215 (1977-07-01), Birney et al.
patent: 4038645 (1977-07-01), Birney et al.
patent: 4042913 (1977-08-01), Birney et al.
patent: 4050060 (1977-09-01), Birney et al.
patent: 4285040 (1981-08-01), Carlson et al.
patent: 4315310 (1982-02-01), Bayliss et al.
patent: 4340932 (1982-07-01), Bakula et al.
patent: 4355355 (1982-10-01), Butwell et al.
patent: 4407016 (1983-09-01), Bayliss et al.
patent: 4446517 (1984-05-01), Katsura et al.
patent: 4649471 (1987-03-01), Briggs et al.
patent: 4677544 (1987-06-01), Kinoshita
patent: 4677546 (1987-06-01), Freeman et al.
patent: 4736290 (1988-04-01), McCallion
patent: 4761736 (1988-08-01), Di Orio
patent: 4761737 (1988-08-01), Duvall et al.
patent: 4797853 (1989-01-01), Savage et al.
patent: 4809217 (1989-02-01), Floro et al.
patent: 4843541 (1989-06-01), Bean et al.
patent: 4847750 (1989-07-01), Daniel
patent: 4849875 (1989-07-01), Fairman et al.
patent: 4864532 (1989-09-01), Reeve et al.
patent: 4926322 (1990-05-01), Stimac et al.
patent: 4942541 (1990-07-01), Hoel et al.
patent: 5023773 (1991-06-01), Baum et al.
patent: 5083259 (1992-01-01), Maresh et al.
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5253308 (1993-10-01), Johnson
patent: 5280579 (1994-01-01), Nye
patent: 5293593 (1994-03-01), Hodge et al.
patent: 5341494 (1994-08-01), Thayer et al.
patent: 5381537 (1995-01-01), Baum et al.
PowerPC 601 Risc Microprocessor Users Manual MPC 601 UM/AD, Chapter 6, Section 6.1, pp. 6-2 through 6-8. Jan. 1993.
PCI Local Bus, Revision 2.0, Apr. 30 1993, "PCI Local Bus Specification", pp. 1-198.
IBM TDB, "Memory Map Protection Circuit", vol. 29, No. 11, Apr. 1987, pp. 4971-4975.
Carpenter Gary D.
Dean Mark E.
Faucher Marc R.
Peterson James C.
Tanner Howard C.
International Business Machines - Corporation
Louis-Jacques Jacques H.
Salys Casimer K.
Teska Kevin J.
LandOfFree
Non-contiguous mapping of I/O addresses to use page protection o does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-contiguous mapping of I/O addresses to use page protection o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-contiguous mapping of I/O addresses to use page protection o will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2337687