Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1997-12-09
2001-02-06
Picardt, Kevin M (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S017000, C324S537000, C324S750010, C324S754120
Reexamination Certificate
active
06184046
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a test apparatus and methodology and more particularly to a test apparatus for performing a non-contact voltage stress test of a semiconductor device in wafer form.
BACKGROUND ART
Semiconductor chips are widely used for many functions in today's electronic world. These semiconductor chips are produced from wafers in a semiconductor manufacturing process. As the final steps of the semiconductor manufacturing process are occurring, a plurality of final test steps are required in order to prevent defective chips from reaching the user. A probe test is a typical test step of this type. In this probe test, a probe test apparatus is used in that probes are brought into physical contact with all of electrical pads of one chip of a large number of semiconductor chips on the semiconductor wafer. A signal pattern is then applied to each of the semiconductor chips by using the probe test apparatus, and an output from each chip is monitored thereby testing the electrical characteristics of each semiconductor chip. With this probe test apparatus, and in order to test all the chips on the semiconductor wafer, a wafer chuck on which the semiconductor wafer is held must be vertically moved up and down and stepped by a distance corresponding to one chip every time a test on one chip is completed.
As the final steps of the semiconductor manufacturing process is completed, a marking step, and a repair step sometimes is performed in addition to the probe test step. In the marking step, a chip determined as a defective chip by the probe test is marked by using ink or the like. In the repair step, a repairable defective chip is repaired. Furthermore as a final test step, a visual test step may be required in which the semiconductor chips on the semiconductor wafer are magnified and visually observed.
As another final test step of the semiconductor manufacturing process, a burn in test is conducted in addition to the above probe test. In that burn in test, semiconductors chips are driven to a state similar to an actual driven state while temperatures and/or voltages stresses are applied to the semiconductor chips thereby finding semiconductor chips which are subject to infant failures of the semiconductor devices manufactured by using the chips. In these conventional systems, this burn in test is not conducted on the semiconductor chip on the semiconductor wafer but is conducted on each of the semiconductor devices obtained by cutting a semiconductor wafer into chips and packaging them at this point more cost has been invested.
A disadvantage of the probe test is that in fact a probe is required to touch the semiconductor wafer. This physical contact with the semiconductor wafer generates particles and the associated damage.
The particles are mainly a problem if probing is attempted on in-process wafers before passivation, especially after an early step like after polysilicon patterning. Therefore, non-contact voltage stressing at these early steps in wafer processing is very advantages or necessary.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus to voltage stress semiconductor wafers without using mechanical or physical contact. The present invention correspondingly generates no or few particles and the corresponding damage.
The present invention uses a grid which is substantially invisible to ultra violet light. This grid is suspended over the semiconductor wafer and avoids physical contact with the semiconductor wafer. A light source is energized to generate a beam of light, and this light is directed to pass through the grid and to the semiconductor wafer. The grid is constructed to be transparent to the light. The grid is energized to a predetermined voltage, and as a consequence defects for example gate oxide defects are stressed and made thereby detectable.
The method can be implemented several ways:
1) The UV/voltage stressing is performed after polysilicon patterning and no observation or defect determination is made until normal wafer electrical test probing. Die with defects induced by the UV/voltage stress result in failure are inked and rejected.
2) A special mask step is introduced before the normal polysilicon patterning that only removes polysilicon from the scribe lines. Thus leaving individual isolated field plates the size of the die. The UV/voltage stressing is then performed. Again no observation or defect determination is made until the normal wafer electrical test probing.
3) The UV/voltage stressing is performed while the wafer is examined with a light emission microscope. Defects emit light and are detected real-time. The applied voltage can be ramped up and defects that show up at different voltages can be identified. This stressing can be of much shorter duration than “1” and “2” above. Defects are observed before they degrade to the point of causing failure. The additional advantage is that defects that would not normally result in failure for the life of the units are not degraded such that they then will result in failure during product use.
Additional objects and advantages of the present invention will be set forth in the description which follows and in part will be obvious from the description or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumalities and combinations particularly pointed out in the attached claims.
REFERENCES:
patent: 4967152 (1990-10-01), Patterson
patent: 5030908 (1991-07-01), Miyoshi et al.
patent: 5150043 (1992-09-01), Flesner
patent: 5508627 (1996-04-01), Patterson
patent: 5963783 (1999-10-01), Lowell et al.
Brady III Wade James
Picardt Kevin M
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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