Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-05-10
2004-03-30
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S265000, C174S266000
Reexamination Certificate
active
06713685
ABSTRACT:
TECHNICAL FIELD
This invention relates to Printed Circuit Boards (PCBs) and particularly to micro-via plated through hole interconnect and shielding structures for PCBs and the method for creating such micro-vias and shielding structures.
BACKGROUND ART
It is always the goal in PCB design to increase the functionality and component capacity. Almost since the inception of PCB's, engineers have striven to add more and more functionality and hence more interconnect traces. These traces go from side to side and from layer to layer and in this way form the interconnect between the “active” electronic elements. The PCB has throughout its lifetime been made from many alternate materials and processes. The most common material being a glass epoxy based laminate, with the PCB builds being of a single sided, double sided or a multilayered (more than 2 layers) configuration. The interconnect medium between layers are created by drilling with mechanical drill through the layers of the PCB exposing the copper interconnect lands on the individual layers. The PCB is then passed through a plating solution and the various layers are connected by plated or deposited copper formed on the interior surface of the drilled through hole. This drilled plated barrel of inter layer interconnect is called a “via”. The most obvious physical attribute is that the via is round when viewed from the top or bottom side. This is caused by “drilling”. Drilling holes through laminate causes a round or circular hole to be created. Drilling of holes is carried out on a drilling machine that drills using a “drill”, a mechanical device that rotates or cuts around its centerline cutting away material about the centerline to create the round or circular holes. The action of a drill is one of cutting.
As mentioned previously more and more interconnect traces have been required as circuit and hence PCB complexity increased. This of course has led to a decrease in size of the vias and an increase in their number. The new smaller vias are called “micro vias” and are typically of a blind nature. Blind vias are vias that do not pass completely through the PCB, but stop at some predetermined layer depth. The smaller via size is required due to an increase in trace density which reduces the points on a given layer where a terminal interconnect land can be positioned such that it aligns with a land on another layer without interference with traces there between. If cross-sectional real estate that a via occupies is reduced, the ability to utilize a via is more likely. However, the decrease in via size has meant that the mechanical drilling of micro vias is almost commercially extinct. Several alternate processes have sprung up namely laser ablation and plasma ablation. Material ablation is an electrochemical reaction to either laser light pulsing or the plasma process. It is not a cutting action or process. However, ablation in like manner removes away material around a centerline.
Ablation emulates mechanical drilling by creating a basically circular hole whichever method is used. This ablated round hole is often described as “drilling” because of removal of material about a centerline, hence the term, Micro via drilling. This round hole has performance level based around the creation of a round or circular shape hole, namely, current carrying capacity, resistance and inductance. For example, a blind via has a lower inductance than a through hole because it has shorter length to the barrel of the via, but its current carrying capacity does not alter because the diameter and hence the circumference of the hole remains the same. Therefore, the current carrying capacity of a via is dependent on the circumferencial length and the conducting medium thickness at the point of interconnection between the trace land and the via.
There are several problems with the conventional circular profile micro-via. For example, when densely populated multi-layer PCBs are utilized there are an enormous amount of traces and interconnects. Circular vias may be a limiting feature if the via is to avoid traces or components when extending through multiple layers because of the cutting area required for a circular hole. Also, the current carrying capacity of circular vias are limited because current carrying capacity of a via is a factor of circumference and thickness of the plating applied to the inner wall. This factor also effects the ability to have multiple traces on a single layer to connect up to the same via because the distance between the contact points are too short thus exceeding the current carrying capacity of the via at those points or the interconnect density at a given land or PCB layer. Conventional standard circular profile micro vias also have a characteristic inductance property due to the spiral nature of the circular via which effects the electron flow through the via resulting in an inductance. The inductance characteristic tends to slow down signal speed and increase noise susceptibility.
Through holes that can possibly be categorized as a Micro-via have been utilized on non-organic silicone based semi-conductor devices to connect two conductive layers separated by an insulation layer where the insulation layer has a contact through hole which exposes a portion of the two conductive surfaces. This through hole embodiment is where one conductive layer continuously extends down through the through-hole thereby electrically connecting the two layers. The semi-conductor via technology has a different purpose and hence a different structure, however it is worth mentioning when discussing via technology (electrical interconnection utilizing a through hole) for completeness. With a semiconductor via the first conductive layer actually conforms to the walls of the through hole and continues over the exposed area of the second layer and in continuous contact with said second layer forming what may be described as a blind via. However the process of forming the via is different from a process where material is cut away about a centerline and there is no plating structure.
In this semi-conductor example the through-hole is filled with a continuation of a first conductive layer of the semi-conductor into the through hole. The through hole structure utilized for semiconductor designs differs from through holes or micro vias utilized for printed circuit boards. First, micro vias for printed circuit boards interconnect a plurality of circuit trace terminal lands or pads by transcending through and exposing them to an interior conductive plating, whereas the semiconductor through hole structure is that of a hole through an insulation layer that separates two layers of conductive media. The interconnection is established by continuously extending one conductive media layer through the through hole establishing contact with the second layer. Establishing a plurality of interconnections to a node created by a via is not the objective in the semiconductor environment as it is with printed circuit board vias.
The specific issue with regard to semi conductor vias is electrical failure of the via structure due to thermal and other stresses particularly in the area around the rim of the opening of the through hole. This is where the conductive media layer begins to extend through the through hole and failures occur because it is at this point that the media layer tends to be thinner. The problem is concentration of stresses in a small area. Whereas, with printed circuit boards the issue with vias is the density of the interconnections as it relates to current carrying capacity and better voltage drop.
DISCLOSURE OF THE INVENTION
It is in view of the above problems that the present invention was developed.
The invention thus has as an object to provide additional current carrying capacity for a via and reduce its inductance characteristic. It is also object of this invention to provide vias that can physically avoid traces and components for densely populated multiple trace multi-layer boards. It is also an object of this invention to connect tra
Cuneo Kamand
Dinh Tuan
Dunlap Codding & Rogers P.C.
Viasystems Group, Inc.
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