Non-blocking peripheral access architecture having a register co

Details Non-blocking peripheral access architecture having a register co Non-blocking peripheral access architecture having a register co

1995-03-28

1998-08-25

Lee, Thomas C.

Multiplex communications

Wide area network

Packet switching

395287, 395308, 395309, 395849, 370351, 370364, G06F 1300

Patent

active

057992070

ABSTRACT:
A computer system is disclosed which has a master, such as a processor, a memory, and I/O device, a first transfer path, which includes a bus, and a second transfer path, which includes a transfer interconnection. Transfers between the memory and the I/O device are effected via the first path while transfers between the processor and the I/O device are transferred via the second path. The disparate treatment between these two types of transfers reduces the likelihood that the transfer via the second path is delayed and thereby reduces the likelihood that the master is totally blocked from operation.

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