Non-binding alignment pin

Details Non-binding alignment pin Non-binding alignment pin

2000-07-26

2003-07-01

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C072S446000, C072S462000

Reexamination Certificate

active

06586957

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an alignment pin for aligning two structures that are to be joined or mated. Specifically, the present invention relates to an alignment pin providing a greatly reduced potential for binding and, more particularly, to a non-binding alignment pin for use in aligning a test head with a semiconductor device handler while docking the test head to the handler.
2. State of the Art
Electrical, functional, and environmental testing is an important facet of semiconductor device manufacturing. Semiconductor devices, such as bare semiconductor die and packaged integrated circuit chips, are routinely subjected to a wide array of tests directed to screening out damaged or defective devices and to measuring the operational characteristics of a device for classification and subsequent sorting. In order to facilitate handling of a large number of semiconductor devices during production, the handling and testing of semiconductor devices is usually automated. Automated equipment for handling, testing, and sorting semiconductor devices is well known in the art.
Shown schematically in
FIG. 1
is an exemplary typical semiconductor device test system
5
. The test system
5
includes a handler
10
and a test head
20
, which are shown in an undocked, or separated, condition. The handler
10
is configured to receive semiconductor devices from a source—for example, a tube or a tray—and to unload the semiconductor devices onto a transport medium, such as a boat. The handler
10
then transports the semiconductor devices to a test station
12
for testing. Also, the handler
10
may thermally condition the semiconductor devices prior to testing. At the test station
12
, the handler
10
positions the semiconductor devices such that leads extending from each individual semiconductor device are in electrical contact with a plurality of test contacts extending from the test head
20
. In order to obtain reliable test data, robust and reliable electrical contact must be maintained between the semiconductor device leads and the test contacts
30
of the test head
20
.
A significant factor affecting the electrical connection between the leads of a semiconductor device and the corresponding test contacts
30
on the test head
20
is alignment between the test head
20
and the handler
10
and, hence, the alignment between the test contacts
30
and the semiconductor device leads. Thus, docking of the test head
20
onto the handler
10
is a critical procedure as the test head
20
, and the test contacts
30
extending therefrom, must be precisely aligned with respect to the handler
10
. Even the slightest misalignment between the handler
10
and test head
20
can result in poor, or even no, electrical contact between the test contacts
30
and the leads of a plurality of semiconductor devices positioned in the test station
12
for testing. Also, the size and weight of the test head
20
are typically very large, often necessitating the use of mechanical lifting equipment for maneuvering the test head
20
during docking. Because of the significant weight of the test head
20
, any misalignment between the test head
20
and handler
10
during a docking operation can result in damage to both the handler
10
and test head
20
, and particularly to the test contacts
30
. Damaged test contacts
30
will, most likely, provide unreliable electrical contact with mating semiconductor device leads.
From the foregoing discussion, one of ordinary skill in the art will understand the importance of maintaining precise alignment between the test head
20
and handler
10
while docking the test head
20
onto the handler
10
. One method for maintaining alignment of the test head
20
relative to the handler
10
is the use of alignment pins
15
, as shown in FIG.
1
. The alignment pins
15
, which are shown attached to the handler
10
, mate with corresponding holes
25
in the test head
20
. Although shown affixed to the handler
10
, the alignment pins
15
may be attached to the test head
20
and, accordingly, the mating holes
25
disposed in the handler
10
. Typically, as shown in
FIG. 1
, two alignment pins
15
are used to provide the necessary alignment between the test head
20
and handler
10
; however, only one alignment pin
15
or more than two alignment pins
15
may be employed. Also, to provide precise alignment between the test head
20
and handler
10
, the design tolerances—size, orientation, and position—of the alignment pins
15
and mating holes
25
are generally relatively small in comparison to the overall dimensions of the test head
20
and handler
10
.
The use of alignment pins
15
, however, may itself cause problems during semiconductor device testing resulting from binding between the alignment pins
15
and mating holes
25
. Generally, binding may be thought of as the braking, or even seizure, of one body relative to another body due to high contact pressure existing between the two bodies. Binding of the alignment pins
15
and mating holes
25
may result in unreliable electrical contact between the test contacts
30
and the leads of a semiconductor device, damage to the test contacts
30
, damage to other portions of the test head
20
and handler
10
, and damage to the semiconductor devices positioned at the test station
12
for testing. Also, binding between the alignment pins
15
and mating holes
25
can make undocking of the test head
20
difficult, as the binding may essentially “lock” the test head
20
to the handler
10
. Further, binding of the alignment pins
15
within the holes
25
can damage the alignment pins
15
themselves, which may exacerbate the effects of binding.
Although the present invention is particularly concerned with the problem of alignment and binding between a semiconductor device handler and test head, as described above, the present invention is applicable to the use of alignment pins to align any types of structures. Thus, the following discussion pertaining to the conditions that may cause binding are generally applicable to the alignment of any two bodies using alignment pins or other alignment structures.
For mating structures, such as an alignment pin and mating hole, binding is generally due to interference between surfaces of the mating structures and can result from any one of a number of interference conditions, or binding modes, that may exist between the surfaces. Binding modes may be generally classified into four types: (1) those due to design or manufacturing tolerances, (2) those due to positioning errors during joining, (3) those due to thermal effects, and (4) those due to wear and damage. The foregoing binding modes, however, are not all-inclusive and those of ordinary skill in the art will understand that binding may result from conditions other than those described herein.
Binding may result from the unwise selection of design tolerances or from the failure to adhere to design tolerances during manufacture. In either case, interference may result between a surface of an alignment pin and a surface of a mating hole. Such interference may, for example, result from an oversized pin, an undersized hole, or, as shown in
FIG. 2
, a circular pin
65
extending from a first body
60
mating with a non-concentric hole
75
in a second body
70
. Errors in feature location tolerances may also lead to binding. Referring to
FIG. 3
, a first body
60
includes a plurality of alignment pins
65
extending transversely therefrom. A second body
70
includes a plurality of holes
75
configured for mating with the alignment pins
65
to align the first and second bodies
60
,
70
. However, due to tolerancing or manufacturing errors, an alignment pin
65
′ and hole
75
′ are out of alignment. For example, the centers of the pin
65
′ and hole
75
′ may be linearly offset by a distance
81
or angularly offset through an angle
91
.
Binding resulting from errors in design and manufacturing tolerances

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