Non-binary memory array

Static information storage and retrieval – Format or disposition of elements

Patent

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Details

36518901, 36518902, 365221, 36523001, G11C 502, G11C 506

Patent

active

050938053

ABSTRACT:
An integrated circuit device having a memory array of memory cells in which the total number N of unique available memory addresses is a power of two, yet wherein neither the number of columns nor the number of rows of cells is a power of two. This permits the chip die size and height/width ratio to be optimized. The device further includes a circuitry for generating address selection signals, providing a total number of unique addresses equal to N, leaving unused some of the memory cells comprising the array.

REFERENCES:
patent: 4047163 (1977-09-01), Choate et al.
patent: 4653050 (1987-03-01), Vaillancourt
patent: 4791607 (1988-12-01), Igarashi et al.
patent: 4945513 (1990-07-01), Ueda
"CMOS BiCMOS Data Book," Cypress Semiconductor, Feb. 1, 1989, pp. 5-48-5-59.

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