Multiplex communications – Channel assignment techniques – Using time slots
Reexamination Certificate
1999-06-11
2004-02-10
Marcelo, Melvin (Department: 2663)
Multiplex communications
Channel assignment techniques
Using time slots
C709S241000, C710S005000, C710S033000
Reexamination Certificate
active
06690676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to computer systems and more particularly to a computer system having a high speed communication link having multiple pipes operating on the communication link.
2. Description of the Related Art
Traditional personal computer architectures partition the computer system into the various blocks shown in the exemplary prior art system illustrated in FIG.
1
. One central feature of this prior art architecture is the use of the Peripheral Component Interface (PCI) bus
101
as the connection between the “north bridge” integrated circuit
103
and the “south bridge” integrated circuit
105
. The north bridge functions generally as a switch connecting CPU
107
, a graphics bus
109
such as the Advanced Graphics Port (AGP) bus, the PCI bus and main memory
111
. The north bridge also contains the memory controller function.
The south bridge generally provides the interface to the input/output (I/O) portion of the system with the possible exception of video output as illustrated in FIG.
1
. Specifically, the south bridge
105
provides a bridge between the PCI bus and legacy PC-AT (Advanced Technology) logic. The south bridge also provides a bridge to the legacy ISA bus
115
, the Integrated Device Electronics (IDE) disk interface
117
and the Universal Serial Bus (USB)
119
. In the illustrated prior art architecture, PCI bus
101
also functions as the major input/output bus for add-in functions such as network connection
121
. The various busses and devices shown in
FIG. 1
are conventional in the personal computer industry and are not described further herein unless necessary for an understanding of the present invention.
In current and future personal computer systems, two basic types of data are transferred between integrated circuits: isochronous data and asynchronous data. Isochronous data refers to data used in real-time data streams such as audio data or motion-picture video data. Asynchronous data is used for all other transfers, such as central processing unit (CPU) accesses to memory and peripherals or bulk data transmissions from a hard drive into system memory.
The PCI bus causes a lack of determinism in the system because any function on the PCI bus can become master of the bus and tie up the bus. Thus, the throughput available on the PCI bus for a particular transfer and the latency that is involved for that transfer is unknown. PCI bus load fluctuations can result in uncertain and irregular quality of service. Therefore, having a PCI bus as the major input/output bus means that the major input/output bus of present day computer systems does not provide proper support for both isochronous and asynchronous data. If a computer system gives asynchronous data priority or treats isochronous data as asynchronous data, then those functions relying on real time data, such as motion-picture video, may not function satisfactorily. Alternatively, if a computer system prioritizes isochronous data, then the performance of the computer system can suffer since the latency of asynchronous data may become unacceptably long. As computer systems are called on to perform more and more real time activity, such as real time video, it becomes more critical that asynchronous and isochronous data be treated in a manner that prevents problems from occurring in the real time tasks without adversely effecting other aspects of computer performance.
In addition, as the number of functions integrated onto the integrated circuits of computer systems increases, the need for additional integrated circuit package pins also increases. Supporting the host bus, the memory interface, the PCI bus and a graphics interface results in a north bridge integrated circuit having a relatively large number of pins that is relatively unpopulated in terms of the number of transistors on the integrated circuit. The large number of pins requires the integrated circuit to be larger than would otherwise be necessary and therefore increases costs.
It would be desirable therefore, to have a deterministic high speed major interconnect bus providing improved quality of service for both isochronous and asynchronous traffic classes. It would also be desirable to reduce the pressure for additional pins on the integrated circuits making up the computer system.
SUMMARY OF THE INVENTION
Accordingly, an interconnection bus is provided in a computer system that carries transactions between functions in the computer system. The protocol of the interconnection bus includes the ability to send a non-addressed transaction request over one of the pipes of a multiple-pipe computer interconnect bus, the multiple pipes carrying transactions on a packet multiplexed basis. In one embodiment, a method is provided for sending a transaction request over the interconnect bus over one of the pipes from a source to a target, the transaction request including a non-addressed transaction command. The method further includes performing a transaction in a predetermined location in response to the non-addressed transaction command and returning a transaction response upon completion of the transaction. The transaction may be a read or write command.
In another embodiment, the invention provides a first integrated circuit including a plurality of first functions. A command packet builder in the first integrated circuit responds to a request from one of the first functions to perform a non-addressed transaction to a second function by providing a non-addressed transaction request packet indicating a non-addressed transaction for the second function. A transmit circuit is coupled to the command packet builder circuit and transmits the non-addressed transaction request packet over an interconnect bus connected to the first integrated circuit. A second integrated circuit is connected to the interconnect bus and includes the second function. A command processing circuit in the second integrated circuit decodes the command received over one of the pipes of the interconnect bus as a command to operate on a predetermined memory area. A response packet builder circuit in the second integrated circuit builds a response indicative of a result of performing the non-addressed transaction command.
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patent: 5742847 (1998-04-01), Knoll et al.
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Marcelo Melvin
Zagorin O'Brien & Graham LLP
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