Noise tolerant phase locked loop

Details Noise tolerant phase locked loop Noise tolerant phase locked loop

2006-08-24

2009-02-10

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C327S005000, C360S051000, C375S376000

Reexamination Certificate

active

07489203

ABSTRACT:
An apparatus and method for providing timing recovery under conditions of low signal to noise ratios (SNRs) is disclosed herein. A preliminary phase error signal is generated by comparing an input signal with a preliminary estimation of an output signal corresponding to the input signal. A correction signal is generated as a function of the output signal, input signal, and preliminary phase error signal. The preliminary phase error signal and the correction signal are combined to generate a final phase error signal.

REFERENCES:
patent: 5757855 (1998-05-01), Strolle et al.
patent: 6236343 (2001-05-01), Patapoutian
patent: 6396788 (2002-05-01), Feyh et al.
patent: 2007/0071152 (2007-03-01), Chen et al.
Nayak, Aravind R. et al. (Aug. 14, 2002) “Lower Bounds for the Performance of Iterative Timing Recovery at Low SNR,” Proceedings of the 15th International Symposium on Mathematical Theory of Networks and Systems, University of Notre Dame, South Bend, Indiana, Aug. 12-16, 10 pages.
Nayak, Aravind (Jun. 2004)Iterative Timing Recovery for Magnetic Recording Channels with Low Signal-to-Noise Ratio, Ph.D. Thesis, School of Electrical and Computer Engineering, Georgia Institute of Technology, 179 pages.

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