Noise tolerant input buffer

Details Noise tolerant input buffer Noise tolerant input buffer

1989-12-20

1991-05-28

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307592, 307594, H03K 522, H03K 1716

Patent

active

050197240

ABSTRACT:
An input buffer interface circuit provides high state and low state input noise tolerance by a tri-state CMOS inverter having high state and low state inputs which are driven conditionally after the propagation of an input signal through predetermined high state and low state delay circuits. In one embodiment, a resettable high state delay circuits is provided by a cascaded combination of NOR gates and inverters, whereby the delay is preempted automatically by an excursion from high to low with the result that the delay path is reinitialized automatically for rejection of successive high state ringing fluctuations. A resettable low state delay circuit is provided by a cascaded combination of NAND gates and inverters.

REFERENCES:
patent: 4710648 (1987-12-01), Hanamura et al.
patent: 4717835 (1988-01-01), Takeuchi
patent: 4760279 (1988-05-01), Saito et al.

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