Noise tolerant CMOS inverter circuit having a resistive bias

Details Noise tolerant CMOS inverter circuit having a resistive bias Noise tolerant CMOS inverter circuit having a resistive bias

1996-09-05

1998-06-16

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Accelerating switching

327206, 327427, H03K 1704, H03K 17687

Patent

active

057677280

ABSTRACT:
A CMOS inverter circuit having a resistive bias device is disclosed. The CMOS inverter circuit comprises a pair of inverter transistors for receiving an input signal. At least one pair of compensating transistors is coupled to the inverter transistors for providing nonlinearity to the input signal. An inverter, coupled to the drains of the inverter transistors at a first node, receives the nonlinear signal as an input. The resistive bias device, coupled to the output of the inverter and to the compensation transistors, provides adjustable reference voltages to the compensation transistors, which allow for an improved noise immunity and high transition gain. The output, taken from the first node, provides for an improvement in the performance of the circuit.

REFERENCES:
patent: 4464587 (1984-08-01), Suzuki et al.
patent: 4539489 (1985-09-01), Vaughn
patent: 4563594 (1986-01-01), Koyama
patent: 5175445 (1992-12-01), Kinugasa et al.
patent: 5341046 (1994-08-01), Crafts
patent: 5459437 (1995-10-01), Campbell
patent: 5594367 (1997-01-01), Campbell

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