Noise suppression interface circuit for non-superimposed two-pha

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307575, 307576, 307577, 307568, 307544, 307579, 307296R, H03K 3013, H03K 19017, H03K 19003

Patent

active

047527048

ABSTRACT:
A noise suppression interface circuit, using field effect transistors of MOS type, for non-superimposed two-phase timing signal generators is described. The upper level and the lower level of the output timing signals are determined by the potentials of two circuit nodes (V.sub.H, V.sub.L) which are respectively coupled, by a first transistor (M1) and a second transistor (M2), operating at saturation, to a first supply terminal (+V.sub.DD) and a second supply terminal (-V.sub.SS) having potentials which are respectively equal and opposite to a common potential. The circuit nodes (V.sub.H, V.sub.L) are both coupled to the common potential by identical number of transistors (M3, M4; M5, M6) each coupled in a diode configuration.

REFERENCES:
patent: 4477736 (1984-10-01), Onishi
patent: 4518873 (1985-05-01), Suzuki et al.
patent: 4527077 (1985-07-01), Higuchi et al.

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