Noise suppressing circuit for VLSI

Details Noise suppressing circuit for VLSI Noise suppressing circuit for VLSI

1993-11-15

1995-07-25

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327373, 327391, 327379, H03K 17687

Patent

active

054365848

ABSTRACT:
A noise suppression circuit for a floating bus in a digital integrated circuit includes pull-up and pull-down feedback loops each connected to the floating bus. The pull-up feedback loop includes a PMOS device connected between a high logic level and the floating bus, with a NOR gate switching the PMOS device. The pull-down feedback loop includes an NMOS device connected between a low logic level and the floating bus, with a NAND gate switches the NMOS device. The NOR and NAND gates are configured such that one of their inputs is connected directly to the floating bus and the other input is connected to the floating bus through an inverter having a finite gate delay. Voltage transitions occurring on the floating bus due to noise injection drive the bus back to its original state before the finite gate delay of the inverter.

REFERENCES:
patent: 4779013 (1988-10-01), Tanaka
patent: 5128555 (1992-07-01), Millman
patent: 5321314 (1994-06-01), Slemmer

Affiliated with

Also associated with

Rating

Noise suppressing circuit for VLSI does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Noise suppressing circuit for VLSI, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Noise suppressing circuit for VLSI will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-742394